Patents Assigned to Library Technologies, Inc.
  • Apparatus and methods for wire load independent logic synthesis and timing closure with constant replacement delay cell libraries
    Publication number: 20030088842
    Abstract: Disclosed is a method of generating an integrated circuit (IC) layout design. An initial layout netlist having a plurality of original cells is provided. A first original cell within the initial layout netlist is replaced with a first replacement cell having a different drive than the first original cell's drive but a same replacement delay as the first original cell when the first original cell is not optimal. The first replacement delay of a particular cell is the particular cell's total delay contribution to a particular delay path that includes the particular cell.
    Type: Application
    Filed: December 18, 2002
    Publication date: May 8, 2003
    Applicant: Library Technologies, Inc.
    Inventor: Mehmet A. Cirit
  • Apparatus and methods for wire load independent logic synthesis and timing closure with constant replacement delay cell libraries
    Patent number: 6523156
    Abstract: Disclosed is a method of generating an integrated circuit (IC) layout design. An initial layout netlist having a plurality of original cells is provided. A first original cell within the initial layout netlist is replaced with a first replacement cell having a different drive than the first original cell's drive but a same replacement delay as the first original cell when the first original cell is not optimal. The first replacement delay of a particular cell is the particular cell's total delay contribution to a particular delay path that includes the particular cell.
    Type: Grant
    Filed: June 8, 2001
    Date of Patent: February 18, 2003
    Assignee: Library Technologies, Inc.
    Inventor: Mehmet A. Cirit