Patents Assigned to LIGHTBITS LABS LTD.
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Patent number: 11513729Abstract: A computer-based system and method for providing a distributed write buffer in a storage system, including: obtaining a write request at a primary storage server to store data associated with the write request in a non-volatile storage of the primary storage server; and storing the data associated with the write request in a persistent memory of the primary storage server or in a persistent memory of an auxiliary storage server based on presence of persistent memory space in the primary storage server. The write request may be acknowledged by the primary storage server after storing the data associated with the write request in the persistent memory of the primary storage server or in the persistent memory of the auxiliary storage server.Type: GrantFiled: July 13, 2021Date of Patent: November 29, 2022Assignee: Lightbits Labs Ltd.Inventors: Shmuel Ben-Yehuda, Ofir Efrati, Abel Alkon Gordon, Ofer Hayut, Eran Kirzner, Alexander Shpiner, Roy Shterman, Maor Vanmak
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Patent number: 11467730Abstract: Systems and methods of managing data storage, on non-volatile memory (NVM) media, by at least one processor may include: receiving a first storage request, to store a first data block on the NVM media; storing content of the first data block on a cache memory module; scheduling a future movement action of the content of the first data block from the cache memory module to the NVM media; and moving, transmitting or copying the content of the first data block from the cache memory module to at least one NVM device of the NVM media, according to the scheduled movement action.Type: GrantFiled: December 31, 2020Date of Patent: October 11, 2022Assignee: LIGHTBITS LABS LTD.Inventors: Shmuel Ben-Yehuda, Ofir Efrati, Abel Alkon Gordon, Ofer Hayut, Eran Kirzner, Alexander Shpiner, Roy Shterman, Maor Vanmak
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Patent number: 11442658Abstract: computer-based system and method for selecting a write unit size for a block storage device, includes performing a plurality of sequences of I/O operations to the block storage device, each sequence having a write unit size from a plurality of write unit sizes; collecting performance metrics of the sequences of I/O operations; and selecting the write unit size for the block storage device from the plurality of write unit sizes based on the performance metrics. In some cases, preconditioning is performed prior to performing the plurality of sequences of I/O operations by emptying the block storage device; and writing data to the block storage device to fill the block storage device above a predetermined level.Type: GrantFiled: May 28, 2021Date of Patent: September 13, 2022Assignee: LIGHTBITS LABS LTD.Inventors: Shmuel Ben-Yehuda, Ofir Efrati, Abel Alkon Gordon, Ofer Hayut, Eran Kirzner, Alexander Shpiner, Roy Shterman, Maor Vanmak
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Patent number: 11385798Abstract: A system and method of managing storage on non-volatile memory (NVM) storage media, by at least one processor, may include receiving, from at least one client computing device, one or more data write requests, associated with application metadata, to store one or more respective data objects on the NVM storage media; performing a first classification of the one or more data objects, based on the application metadata, so as to associate each data object to a group of data objects; storing the data objects of each group in a dedicated storage set of a logical address space; and transmitting, or copying the data objects of each storage set to be stored in a respective, dedicated range of the NVM storage media.Type: GrantFiled: December 28, 2020Date of Patent: July 12, 2022Assignee: Lightbits Labs Ltd.Inventor: Maor Vanmak
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Patent number: 11256431Abstract: A field programmable gate array (FPGA), that includes a trusted FPGA logic, an untrusted FPGA logic and a monitor; wherein the monitor is configured to monitor the untrusted FPGA logic and prevent the untrusted FPGA logic from violating predefined constrains imposed on an operation of the untrusted FPGA logic; wherein the predefined constraints are stored in a memory region of the FPGA that is not accessible to the untrusted FPGA logic.Type: GrantFiled: December 29, 2017Date of Patent: February 22, 2022Assignee: LIGHTBITS LABS LTD.Inventors: Shmuel Ben-Yehuda, Ofir Efrati, Sagi Grimberg, Eran Kirzner, Ziv Tishel, Fabian Trumper
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Patent number: 11093408Abstract: A system and a method of managing storage of cached data objects on a non-volatile memory (NVM) computer storage media including at least one NVM storage device, by at least one processor, may include: receiving one or more data objects having respective Time to Live (TTL) values; storing the one or more data objects and respective TTL values at one or more physical block addresses (PBAs) of the storage media; and performing a garbage collection (GC) process on one or more PBAs of the storage media based on at least one TTL value stored at a PBA of the storage media.Type: GrantFiled: June 3, 2019Date of Patent: August 17, 2021Assignee: Lightbits Labs Ltd.Inventors: Alexander Solganik, Adir Gabai, Shmuel Ben-Yehuda, Eran Kirzner, Abel Alkon Gordon
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Patent number: 11074173Abstract: A system and a method of managing over-provisioning (OP) on non-volatile memory (NVM) computer storage media including at least one NVM storage device, by at least one processor, may include: receiving a value of one or more run-time performance parameters pertaining to data access requests to one or more physical block addresses (PBAs) of the storage media; receiving at least one of a target performance parameter value and a system-inherent parameter value; analyzing the received at least one run-time performance parameter value, to determine an optimal OP ratio of at least one NVM storage device in view of the received at least of a target performance parameter value and system-inherent parameter value; and limiting storage of data objects on the at least one NVM storage device according to the determined OP ratio.Type: GrantFiled: June 24, 2019Date of Patent: July 27, 2021Assignee: Lightbits Labs Ltd.Inventor: Abel Alkon Gordon
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Patent number: 11036626Abstract: A system and a method of managing over-provisioning (OP) on non-volatile memory (NVM) computer storage media including at least one NVM storage device, by at least one processor, may include: receiving a value of one or more run-time performance parameters pertaining to data access requests to one or more physical block addresses (PBAs) of the storage media; receiving at least one of a target performance parameter value and a system-inherent parameter value; analyzing the received at least one run-time performance parameter value, to determine an optimal OP ratio of at least one NVM storage device in view of the received at least of a target performance parameter value and system-inherent parameter value; and limiting storage of data objects on the at least one NVM storage device according to the determined OP ratio.Type: GrantFiled: June 24, 2019Date of Patent: June 15, 2021Assignee: Lightbits Labs Ltd.Inventor: Abel Alkon Gordon
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Patent number: 10990447Abstract: A method and a system for controlling the access of a plurality of client computers to storage media, the system including: a processor, a Random-Access Memory (RAM) device; and a Network Interface Controller (NIC), configured to establish a plurality of connections with the clients. The processor may dynamically allocate a buffer memory space to each connected client computer on the RAM device, and the NIC may be configured to receive at least one storage access request from at least one client, over at least one computer network connection. The RAM device may accumulate data of the at least one storage access request in the buffer allocated to the respective connected client computer, and the processor may be configured, upon completion of the accumulation of data, to propagate the buffered data to at least one storage device of the storage media.Type: GrantFiled: July 12, 2018Date of Patent: April 27, 2021Assignee: Lightbits Labs Ltd.Inventors: Alexander Shpiner, Abel Alkon Gordon, Sagi Grimberg
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Patent number: 10963393Abstract: A method for accessing a storage system, the method may include receiving a block call, from a processor that executes an application and by a storage engine of a computer that is coupled to a storage system; generating, by the storage engine and based on the block call, a key value call; and sending the key value call to a key value frontend of the storage system.Type: GrantFiled: December 29, 2017Date of Patent: March 30, 2021Assignee: Lightbits Labs Ltd.Inventors: Shmuel Ben-Yehuda, Ofir Efrati, Abel Alkon Gordon, Eran Kirzner, Fabian Trumper
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Patent number: 10956346Abstract: A storage system that includes an in-line hardware accelerator, a solid-state drive (SSD) unit, a central processing unit (CPU), a volatile memory module, and an accelerator memory module that is coupled to the in-line hardware accelerator or belongs to the in-line hardware accelerator; wherein the in-line hardware accelerator is directly coupled to the SSD unit, the volatile memory and the non-volatile memory; wherein the CPU is directly coupled to the volatile memory and to the non-volatile memory; wherein the in-line hardware accelerator is configured to manage access to the SSD unit; wherein the in-line accelerator is configured to retrieve data stored in the volatile memory module and the non-volatile memory module without involving the CPU.Type: GrantFiled: December 29, 2017Date of Patent: March 23, 2021Assignee: Lightbits Labs Ltd.Inventors: Shmuel Ben-Yehuda, Ofir Efrati, Sagi Grimberg, Eran Kirzner, Ziv Tishel, Fabian Trumper
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Patent number: 10713162Abstract: A method and a system for accelerating computer data garbage collection (GC) on a non-volatile memory (NVM) computer storage device may include: monitoring, by a processor, a data validity parameter of at least one physical write unit (PWU), where the PWU may include a plurality of physical data pages of the NVM device; sending at least one GC command from the processor to an accelerator associated with the NVM device, based on the monitored data validity parameter; copying, by the accelerator, a plurality of data-objects stored on at least one first PWU, to a read address space comprised within the accelerator; copying valid data-objects from the read address space to a write address space comprised within the accelerator until the amount of data in the write address space exceeds a predefined threshold; and storing, by the accelerator, the data content in at least one second PWU in the NVM media.Type: GrantFiled: April 26, 2018Date of Patent: July 14, 2020Assignee: Lightbits Labs Ltd.Inventors: Shmuel Ben-Yehuda, Ofir Efrati, Roy Geron, Abel Alkon Gordon, Sagi Grimberg, Eran Kirzner, Ziv Tishel, Maor Vanmak, Ofer Hayut
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Patent number: 10684964Abstract: A system and a method for reducing read latency of a storage media associated with at least one host computer, by at least one processor, may include assigning each storage segment of the non-volatile storage to a first Read-Latency Set (RLS) and a second RLS, wherein the first RLS is attributed a read/write mode and the second RLS is attributed a read-only mode; receiving read-requests and write-requests from the at least one host computer, wherein each of said requests is attributed a priority; and serving the received requests according to RLS work modes and according to the priority of each request.Type: GrantFiled: August 1, 2018Date of Patent: June 16, 2020Assignee: Lightbits Labs Ltd.Inventors: Abel Alkon Gordon, Sagi Grimberg, Shmuel Ben-Yehuda
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Patent number: 10642733Abstract: A system and a method of balancing a load of access of at least one computing device to an arbitrary integer number of connected memory devices associated with a memory cluster address space, the method including: determining, by a controller, a number N corresponding to an arbitrary integer number of memory devices connected to a plurality of memory interfaces, wherein N is between 1 and the number of memory interfaces; receiving, by the controller, at least one data object, corresponding to an original processor address (OPA) from the at least one computing device; computing, by the controller, at least one interleaving function according to N; and mapping, by an interleaving circuit, the OPA to a memory cluster address (MCA), according to the at least one interleaving function, so that the data object is equally interleaved among the N connected devices.Type: GrantFiled: July 12, 2018Date of Patent: May 5, 2020Assignee: LIGHTBITS LABS LTD.Inventor: Ofer Hayut
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Patent number: 10628301Abstract: A system and method of managing non-volatile computer storage media may include: receiving at least one value of at least one parameter, including for example: a size of data objects, a frequency of data write requests, a size of write units (WUs) and a required write amplification value; setting a cyclic write pointer to point to a WU having a logical address space; setting a cyclic garbage collection (GC) pointer to point to a WU having a logical address space, located ahead of the WU pointed by the write pointer; performing GC on the WU pointed by the GC pointer; and incrementing the cyclic GC pointer to point to a next WU according to the value of the cyclic write pointer and according to the at least one received parameter value.Type: GrantFiled: June 21, 2018Date of Patent: April 21, 2020Assignee: Lightbits Labs Ltd.Inventors: Shmuel Ben-Yehuda, Ofir Efrati, Abel Alkon Gordon, Sagi Grimberg, Eran Kirzner, Maor Vanmak
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Patent number: 10552349Abstract: A method and a system for pipelining read transactions of a host computer from a storage module, including: transferring from a host computer to an accelerator a read list, including at least one pointer to a data block stored on the storage module, and a respective data block size; sending an acknowledgement to the host; fetching at least one data block by the accelerator from the storage module, and writing it to a staging buffer in a sequential order; sending at least one read request from the host computer to the accelerator, relating to at least one requested data block. If the data block is available on the staging buffer, then sending the corresponding data to the host from the staging buffer. Otherwise the read response is delayed until the requested data is fetched from the storage module.Type: GrantFiled: June 14, 2018Date of Patent: February 4, 2020Assignee: LIGHTBITS LABS LTD.Inventors: Amir Shavit, Roy Geron