Patents Assigned to LIGHTBITS LABS LTD.
  • Patent number: 11789632
    Abstract: In a storage system including a first tier and a second tier a method includes: storing access statistics per object; obtaining a request to perform a write operation; calculating a recency factor to the first object based on the access statistics; and writing the first object to one of the first tier and the second tier, depending on the recency factor. Performing garbage collection process on the second tier may include: reading metadata of an object stored in the second tier; determining whether the object is valid based on the metadata; if the object is invalid, discarding the object; and if the second object is valid: calculating a recency factor for the object based on the access statistics of the object; and moving the object to the first tier or leaving the object in the second tier, depending on the recency factor of the second object.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: October 17, 2023
    Assignee: LIGHTBITS LABS LTD.
    Inventors: Shmuel Ben-Yehuda, Ofir Efrati, Abel Alkon Gordon, Ofer Hayut, Eran Kirzner, Alexander Shpiner, Roy Shterman, Maor Vanmak
  • Patent number: 11740804
    Abstract: A system and method for performing data striping and data protection, may include: obtaining, in a network interface controller (NIC) from a host processor, a command to store data in a storage system, wherein the host processor is connected to a network through the NIC; dividing, by the NIC, the data into a plurality of portions; mapping, by the NIC, each of the plurality of portions to at least one of a plurality of storage targets, wherein the plurality of storage targets are connected to the NIC over the network; and, transferring, by the NIC, each of the plurality of portions to the mapped at least one storage target.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: August 29, 2023
    Assignee: LIGHTBITS LABS LTD.
    Inventor: Abel Alkon Gordon
  • Patent number: 11714767
    Abstract: A system and method for performing a combined storage operation, the method including using a direct memory access (DMA) controller to obtain a modified DMA command, wherein the modified DMA command includes parameters of a data manipulation and one of a user read command or a user write command; retrieve data according to the user read command or the user write command; manipulate the data according to the parameters of a data manipulation, inline with the user read command or the user write command; and transmit the manipulated data according to the user read command or the user write command.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: August 1, 2023
    Assignee: LIGHTBITS LABS LTD.
    Inventors: Roii Goldstein, Ofer Hayut, Roy Geron
  • Patent number: 11467730
    Abstract: Systems and methods of managing data storage, on non-volatile memory (NVM) media, by at least one processor may include: receiving a first storage request, to store a first data block on the NVM media; storing content of the first data block on a cache memory module; scheduling a future movement action of the content of the first data block from the cache memory module to the NVM media; and moving, transmitting or copying the content of the first data block from the cache memory module to at least one NVM device of the NVM media, according to the scheduled movement action.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: October 11, 2022
    Assignee: LIGHTBITS LABS LTD.
    Inventors: Shmuel Ben-Yehuda, Ofir Efrati, Abel Alkon Gordon, Ofer Hayut, Eran Kirzner, Alexander Shpiner, Roy Shterman, Maor Vanmak
  • Patent number: 11442658
    Abstract: computer-based system and method for selecting a write unit size for a block storage device, includes performing a plurality of sequences of I/O operations to the block storage device, each sequence having a write unit size from a plurality of write unit sizes; collecting performance metrics of the sequences of I/O operations; and selecting the write unit size for the block storage device from the plurality of write unit sizes based on the performance metrics. In some cases, preconditioning is performed prior to performing the plurality of sequences of I/O operations by emptying the block storage device; and writing data to the block storage device to fill the block storage device above a predetermined level.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: September 13, 2022
    Assignee: LIGHTBITS LABS LTD.
    Inventors: Shmuel Ben-Yehuda, Ofir Efrati, Abel Alkon Gordon, Ofer Hayut, Eran Kirzner, Alexander Shpiner, Roy Shterman, Maor Vanmak
  • Patent number: 11256431
    Abstract: A field programmable gate array (FPGA), that includes a trusted FPGA logic, an untrusted FPGA logic and a monitor; wherein the monitor is configured to monitor the untrusted FPGA logic and prevent the untrusted FPGA logic from violating predefined constrains imposed on an operation of the untrusted FPGA logic; wherein the predefined constraints are stored in a memory region of the FPGA that is not accessible to the untrusted FPGA logic.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: February 22, 2022
    Assignee: LIGHTBITS LABS LTD.
    Inventors: Shmuel Ben-Yehuda, Ofir Efrati, Sagi Grimberg, Eran Kirzner, Ziv Tishel, Fabian Trumper
  • Patent number: 10642733
    Abstract: A system and a method of balancing a load of access of at least one computing device to an arbitrary integer number of connected memory devices associated with a memory cluster address space, the method including: determining, by a controller, a number N corresponding to an arbitrary integer number of memory devices connected to a plurality of memory interfaces, wherein N is between 1 and the number of memory interfaces; receiving, by the controller, at least one data object, corresponding to an original processor address (OPA) from the at least one computing device; computing, by the controller, at least one interleaving function according to N; and mapping, by an interleaving circuit, the OPA to a memory cluster address (MCA), according to the at least one interleaving function, so that the data object is equally interleaved among the N connected devices.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: May 5, 2020
    Assignee: LIGHTBITS LABS LTD.
    Inventor: Ofer Hayut
  • Patent number: 10552349
    Abstract: A method and a system for pipelining read transactions of a host computer from a storage module, including: transferring from a host computer to an accelerator a read list, including at least one pointer to a data block stored on the storage module, and a respective data block size; sending an acknowledgement to the host; fetching at least one data block by the accelerator from the storage module, and writing it to a staging buffer in a sequential order; sending at least one read request from the host computer to the accelerator, relating to at least one requested data block. If the data block is available on the staging buffer, then sending the corresponding data to the host from the staging buffer. Otherwise the read response is delayed until the requested data is fetched from the storage module.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: February 4, 2020
    Assignee: LIGHTBITS LABS LTD.
    Inventors: Amir Shavit, Roy Geron