Abstract: An apparatus having a segmented optical modulator includes an optical waveguide having three or more segments. Each of three or more optical modulators includes a corresponding waveguide segment and is configured to apply an optical modulation that is proportional to the length of the segment. Three or more electrical contacts receive respective bit values of binary values. Each binary value includes at least three bit values including a least significant bit (LSB) bit value, a most significant bit (MSB) bit value, and at least one intermediate bit (IB) bit value between the LSB bit value and the MSB bit value. At least one waveguide segment of a corresponding optical modulator receiving an LSB bit value is positioned between a first waveguide segment of a corresponding optical modulator receiving an MSB bit value and a second waveguide segment of a corresponding optical modulator receiving an IB bit value.
Abstract: An integrated circuit interposer includes a semiconductor substrate layer; a first metal contact layer including a first metal contact section that includes metal contacts arranged for electrically coupling to a first semiconductor die in a controlled collapsed chip connection, and a second metal contact section that includes metal contacts arranged for electrically coupling to a second semiconductor die in a controlled collapsed chip connection. A first patterned layer includes individually photomask patterned metal path sections. A second patterned layer includes individually photomask patterned waveguide sections, including a first waveguide that crosses at least one boundary between individually photomask patterned waveguide sections.
Type:
Grant
Filed:
July 6, 2021
Date of Patent:
June 27, 2023
Assignee:
Lightelligence, Inc.
Inventors:
Huaiyu Meng, Cheng-Kuan Lu, Jonathan Terry, Jingdong Deng, Maurice Steinman, Gilbert Hendry, Yichen Shen
Abstract: Data to be processed includes vector element values of an input vector and matrix element values of a model matrix associated with a neural network model. A vector-matrix multiplication module receives a set of matrix element values for performing a vector-matrix multiplication operation. Processing the data includes computing a plurality of intermediate vectors based on element-wise vector multiplication between different subsets of the vector element values and different respective pre-processing vectors. The vector-matrix multiplication module is loaded with a core matrix, and the input vector is multiplied by the model matrix based on separately multiplying each of the intermediate vectors by the loaded core matrix.
Type:
Grant
Filed:
November 11, 2022
Date of Patent:
May 23, 2023
Assignee:
Lightelligence, Inc.
Inventors:
Matthew Raja Khoury, Rumen Rumenov Dangovski, Longwu Ou, Yichen Shen, Li Jing
Abstract: Data to be processed includes vector element values of an input vector and matrix element values of a model matrix associated with a neural network model. A vector-matrix multiplication module receives a set of matrix element values for performing a vector-matrix multiplication operation. Processing the data includes computing a plurality of intermediate vectors based on element-wise vector multiplication between different subsets of the vector element values and different respective pre-processing vectors. The vector-matrix multiplication module is loaded with a core matrix, and the input vector is multiplied by the model matrix based on separately multiplying each of the intermediate vectors by the loaded core matrix.
Type:
Grant
Filed:
January 31, 2020
Date of Patent:
December 13, 2022
Assignee:
Lightelligence, Inc.
Inventors:
Matthew Raja Khoury, Rumen Rumenov Dangovski, Longwu Ou, Yichen Shen, Li Jing