Patents Assigned to LightFleet Corporation
  • Patent number: 11516143
    Abstract: Operating a computer network uses a routing and control protocol, the computer network having an interconnect fabric including routing and control distribution devices and fabric interface devices, each of the routing and control distribution devices and each of the fabric interface devices having a state machine having an input processing unit having parallel input buffers, an output processing unit having parallel output buffers and an arbiter; operating the state machine based on a set of instructions and a table located at the state machine; transferring data from the input processing unit to the output processing unit; choosing a highest priority currently flit occupied parallel input buffer located in the input processing unit for data transmission on a highest priority currently flit occupied channel; and; interrupting the highest currently flit occupied priority channel when one of the parallel input buffers is detected to contain a superseding even higher priority flit.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: November 29, 2022
    Assignee: Lightfleet Corporation
    Inventor: William B. Dress
  • Patent number: 11418593
    Abstract: A data distribution system includes a data distribution module and at least two host-bus adapters coupled to the data distribution module. The data distribution system includes a memory-management system including a plurality of memory regions. The memory-management system is coherent across the plurality of memory regions and an absolute address of each of the plurality of memory regions accessed by a same offset.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: August 16, 2022
    Assignee: Lightfleet Corporation
    Inventor: William Dress
  • Patent number: 11343197
    Abstract: Switchless interconnect fabric message distribution includes end-to-end partitioning of message pathways or multiple priority levels with interrupt capability. A switchless interconnect fabric message distribution system includes a data distribution module and at least two host-bus adapters connected to the data distribution module. The data distribution module includes partition first in first out buffers. Each of the host-bus adapters includes an input manager connected to input priority first in first out buffers and an output manager connected to priority first in first out buffers.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: May 24, 2022
    Assignee: Lightfleet Corporation
    Inventors: William Dress, Aaron LeClaire
  • Patent number: 11228458
    Abstract: Operating a data distribution including a data distribution module and a plurality of host-bus adapters coupled to the data distribution module can include defining a coherent group that includes a set of members that includes the plurality of host-bus adapters; providing a group-coherent memory area in each of the set of members; and initiating a one-to-all broadcast message from a one of the plurality of host-bus adapters to all of the set of members when the one of the plurality of host-bus adapters requests a write to its local group-coherent memory area. The group-coherent memory area in each of the set of members is physically mirrored with a temporal coherence and no semaphores or access enables are required to achieve the temporal coherence of the coherent group.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: January 18, 2022
    Assignee: Lightfleet Corporation
    Inventor: William Dress
  • Patent number: 11184290
    Abstract: A parallel multicast star topology data network includes a plurality of input buffers, a first arbitration mechanism coupled to the plurality of input buffers, a plurality of output buffers coupled to the first arbitration mechanism and a plurality of interconnect exits coupled to the plurality of output buffers. When packet contents of a multicast message are ready for release from the first arbitration mechanism then all of the packet contents are substantially simultaneously released to the plurality of output buffers and then substantially simultaneously to the plurality of interconnect exits.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: November 23, 2021
    Assignee: Lightfleet Corporation
    Inventor: William Dress
  • Publication number: 20210211388
    Abstract: Operating a computer network uses a routing and control protocol, the computer network having an interconnect fabric including routing and control distribution devices and fabric interface devices, each of the routing and control distribution devices and each of the fabric interface devices having a state machine having an input processing unit having parallel input buffers, an output processing unit having parallel output buffers and an arbiter; operating the state machine based on a set of instructions and a table located at the state machine; transferring data from the input processing unit to the output processing unit; choosing a highest priority currently flit occupied parallel input buffer located in the input processing unit for data transmission on a highest priority currently flit occupied channel; and; interrupting the highest currently flit occupied priority channel when one of the parallel input buffers is detected to contain a superseding even higher priority flit.
    Type: Application
    Filed: January 11, 2021
    Publication date: July 8, 2021
    Applicant: Lightfleet Corporation
    Inventor: William B. Dress
  • Publication number: 20210160321
    Abstract: A data distribution system includes a data distribution module and at least two host-bus adapters coupled to the data distribution module. The data distribution system includes a memory-management system including a plurality of memory regions. The memory-management system is coherent across the plurality of memory regions and an absolute address of each of the plurality of memory regions accessed by a same offset.
    Type: Application
    Filed: February 1, 2021
    Publication date: May 27, 2021
    Applicant: Lightfleet Corporation
    Inventor: William Dress
  • Publication number: 20200412661
    Abstract: Switchless interconnect fabric message distribution includes end-to-end partitioning of message pathways or multiple priority levels with interrupt capability. A switchless interconnect fabric message distribution system includes a data distribution module and at least two host-bus adapters connected to the data distribution module. The data distribution module includes partition first in first out buffers. Each of the host-bus adapters includes an input manager connected to input priority first in first out buffers and an output manager connected to priority first in first out buffers.
    Type: Application
    Filed: September 16, 2020
    Publication date: December 31, 2020
    Applicant: Lightfleet Corporation
    Inventors: William Dress, Aaron LeClaire
  • Publication number: 20200358709
    Abstract: A parallel multicast star topology data network includes a plurality of input buffers, a first arbitration mechanism coupled to the plurality of input buffers, a plurality of output buffers coupled to the first arbitration mechanism and a plurality of interconnect exits coupled to the plurality of output buffers. When packet contents of a multicast message are ready for release from the first arbitration mechanism then all of the packet contents are substantially simultaneously released to the plurality of output buffers and then substantially simultaneously to the plurality of interconnect exits.
    Type: Application
    Filed: July 28, 2020
    Publication date: November 12, 2020
    Applicant: Lightfleet Corporation
    Inventor: William Dress
  • Publication number: 20200267019
    Abstract: Operating a data distribution including a data distribution module and a plurality of host-bus adapters coupled to the data distribution module can include defining a coherent group that includes a set of members that includes the plurality of host-bus adapters; providing a group-coherent memory area in each of the set of members; and initiating a one-to-all broadcast message from a one of the plurality of host-bus adapters to all of the set of members when the one of the plurality of host-bus adapters requests a write to its local group-coherent memory area. The group-coherent memory area in each of the set of members is physically mirrored with a temporal coherence and no semaphores or access enables are required to achieve the temporal coherence of the coherent group.
    Type: Application
    Filed: February 24, 2020
    Publication date: August 20, 2020
    Applicant: Lightfleet Corporation
    Inventor: William Dress
  • Publication number: 20190372904
    Abstract: Operating a computer network uses a routing and control protocol, the computer network having an interconnect fabric including routing and control distribution devices and fabric interface devices, each of the routing and control distribution devices and each of the fabric interface devices having a state machine having an input processing unit having parallel input buffers, an output processing unit having parallel output buffers and an arbiter; operating the state machine based on a set of instructions and a table located at the state machine; transferring data from the input processing unit to the output processing unit; choosing a highest priority currently flit occupied parallel input buffer located in the input processing unit for data transmission on a highest priority currently flit occupied channel; and; interrupting the highest currently flit occupied priority channel when one of the parallel input buffers is detected to contain a superseding even higher priority flit.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 5, 2019
    Applicant: Lightfleet Corporation
    Inventor: William B. Dress
  • Patent number: 10153925
    Abstract: A multidimensional symbol encoder is coupled to a transmitter. Multidimensional symbols are encoded by concatenating two or more partial symbols, wherein individual intervals of up and down sections of the two or more partial symbols are independently controlled as to duration. A multidimensional symbol decoder is coupled to a receiver. Multidimensional symbols are decoded by measuring duration of individual intervals i) that are independently controlled as to duration and ii) that are up and down sections of two or more concatenated partial symbols.
    Type: Grant
    Filed: September 27, 2014
    Date of Patent: December 11, 2018
    Assignee: Lightfleet Corporation
    Inventor: William B. Dress
  • Publication number: 20170244583
    Abstract: Methods and apparatus are described for time domain signals. An apparatus includes an electrical circuit coupled to a transmitter which conducts a bit stream of electrical, light or other photonic pulses into an apparatus encoder.
    Type: Application
    Filed: May 6, 2017
    Publication date: August 24, 2017
    Applicant: Lightfleet Corporation
    Inventor: William B. Dress
  • Publication number: 20170244584
    Abstract: Methods and apparatus are described for time domain signals. An apparatus includes an electrical circuit decoder coupled to a receiver.
    Type: Application
    Filed: May 6, 2017
    Publication date: August 24, 2017
    Applicant: Lightfleet Corporation
    Inventor: William B Dress
  • Patent number: 9674116
    Abstract: A method includes operating a packet flow module including a plurality of ports, each of the plurality of ports including at least a pair of bidirectional and logically independent communications channels. An apparatus includes a packet flow module including a plurality of ports, each of the plurality of ports including at least a pair of bidirectional and logically independent communications channels.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: June 6, 2017
    Assignee: Lightfleet Corporation
    Inventor: William Dress
  • Patent number: 9590735
    Abstract: A modular interconnect includes an mn-by-mn fully connected, direct broadcast, point-to-point, all-to-all interconnect fabric, wherein the mn-by-mn fully connected, direct broadcast, point-to-point, all-to-all interconnect fabric is non-blocking and congestion free, and wherein m is an integer?2 and n is an integer?2. Operating the modular interconnect includes distributing each of mn inputs to each and every one of mn outputs.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: March 7, 2017
    Assignee: Lightfleet Corporation
    Inventor: William B Dress
  • Patent number: 8909047
    Abstract: A modular interconnect includes an mn-by-mn fully connected, direct broadcast, point-to-point, all-to-all interconnect fabric, wherein the mn-by-mn fully connected, direct broadcast, point-to-point, all-to-all interconnect fabric is non-blocking and congestion free, and wherein m is an integer?2 and n is an integer?2. Operating the modular interconnect includes distributing each of mn inputs to each and every one of mn outputs.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: December 9, 2014
    Assignee: LightFleet Corporation
    Inventor: William B Dress
  • Publication number: 20140314099
    Abstract: A method includes operating a packet flow module including a plurality of ports, each of the plurality of ports including at least a pair of bidirectional and logically independent communications channels. An apparatus includes a packet flow module including a plurality of ports, each of the plurality of ports including at least a pair of bidirectional and logically independent communications channels.
    Type: Application
    Filed: March 21, 2013
    Publication date: October 23, 2014
    Applicant: LightFleet Corporation
    Inventor: LightFleet Corporation
  • Patent number: 8848808
    Abstract: Methods and apparatus are described for time domain signals. A method includes creating a bipolar pulse whose high (up) and low (down) periods are separately and precisely controllable.
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: September 30, 2014
    Assignee: Lightfleet Corporation
    Inventor: William Benjamin Dress
  • Patent number: 8229006
    Abstract: Pulse communications using precision timing includes detecting a pulse stream from a pulse code modulated carrier signal; transforming the pulse stream into a reshaped pulse stream; transforming the reshaped pulse stream into a counter gate stream; and recovering a data stream from the counter gate stream. The reshaped pulse stream is transformed into the counter gate stream with a digital circuit.
    Type: Grant
    Filed: February 25, 2009
    Date of Patent: July 24, 2012
    Assignee: Lightfleet Corporation
    Inventors: William B. Dress, Brian Donovan