Patents Assigned to Lightspeed Semiconductor Corporation
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Patent number: 7102237Abstract: Disclosed herein is an integrated circuit customized by mask programming using custom conducting layers and via layers interspersed with the custom conducting layers, where the via layers are defined by masks designed prior to receiving a custom circuit design.Type: GrantFiled: May 28, 2003Date of Patent: September 5, 2006Assignee: Lightspeed Semiconductor CorporationInventor: Eric Dellinger
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Patent number: 6954917Abstract: A method for forming an application specific integrated circuit, comprises receiving a circuit design for the application specific integrated circuit from a designer; performing an initial place and route layout of the circuit design which leaves a group of buffer modules unused, based upon a partially predesigned integrated circuit, in which the partially predesigned integrated circuit includes a plurality of logic modules and a plurality of buffer modules uniformly distributed amongst the logic modules; evaluating load and timing characteristics for the initial place and route layout of the circuit design; and integrating buffer modules from the group of unused buffer modules into the circuit design, based on the load and timing characteristics evaluated.Type: GrantFiled: June 11, 2003Date of Patent: October 11, 2005Assignee: Lightspeed Semiconductor CorporationInventors: Dana How, Adi Srinivasan, Abbas El Gamal
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Patent number: 6885043Abstract: An embodiment of the invention includes a routing architecture with a plurality of predesigned layers and a custom layer. The structure includes a plurality of parallel vertical tracks. In one layer, the tracks include a pin coupled to an input/output of an underlying function block and the track also includes a first portion of an unbroken conductive path. A second portion of the unbroken conductive path is formed under the pin in at least a second predesigned layer. In some embodiments, the second portion of the unbroken conductive path is formed in the second predesigned layer for some tracks and a third predesigned layer for other tracks. Hence, pins and unbroken conductive paths are multiplexed in a single track. In addition, the second predesigned layer further includes long horizontal conductors.Type: GrantFiled: January 18, 2002Date of Patent: April 26, 2005Assignee: Lightspeed Semiconductor CorporationInventors: Lyle Smith, Eric Dellinger, Eric West, Shridhar Mukund
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Patent number: 6861867Abstract: A system for remotely/automatedly testing an ASIC and particularly to testing a user-designed circuit is disclosed. In general, a system in accordance with the invention includes a plurality of cells, where the cells are couplable to form a user-designed circuit, e.g., by customizing routing. Within the ASIC and prior to any knowledge of the user-designed circuit, the ASIC includes circuitry to enable internal remote/automated testing of the user-designed circuit to be later formed. The circuitry controls the input and mode of operation of the cells and the sequencing of multiple synchronous or asynchronous clock domain inputs thereby providing testing of the user-designed circuit at speed for stuck-at-faults and delay faults.Type: GrantFiled: March 7, 2002Date of Patent: March 1, 2005Assignee: Lightspeed Semiconductor CorporationInventors: Eric West, Shridhar Mukund
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Patent number: 6804812Abstract: A programmable logic array (PLA) in accordance with the invention achieves a maximum amount of depopulation of programmable connections while still implementing a logic function and maintaining flexibility for future reprogramming. In addition, a PLA in accordance with the invention can be built so that no matter what functionality is programmed, performance characteristics for the device are maintained. Further, a PLA in accordance with the invention does not require a regular array structure.Type: GrantFiled: June 10, 2003Date of Patent: October 12, 2004Assignee: Lightspeed Semiconductor CorporationInventors: Robert Osann, Jr., Patrick Hallinan, Jung Lee, Shridhar Mukund
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Patent number: 6770949Abstract: A system and method in accordance with the invention minimizes the redesign burden in tuning and/or customizing PLLs on ICs. Variable resistors are placed in the PLL in places that facilitate tuning. The variable resistors are formed with a set of at least three contacts, where each contact is in electrical communication with a resistive area. A metal layer is used to form leads to the resistive area, where each lead is formed to be in electrical communication with only a selected subset of contacts from the set. In one embodiment, only the uppermost metal layer used in forming the IC is used to form the leads. Because the uppermost metal layer is utilized, the resistor value can be adjusted simply by selecting the subsets of contacts that are to be in electrical communication with the uppermost metal layer. In this manner, only one metal layer needs to be adjusted in tuning and/or customizing a PLL, rather than having to redesign and re-layout all metal layers and vias in the IC.Type: GrantFiled: August 31, 1998Date of Patent: August 3, 2004Assignee: Lightspeed Semiconductor CorporationInventor: Shafy Eltoukhy
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Patent number: 6769109Abstract: In accordance with the invention, a method for customizing a one-time configurable integrated circuit to include a multi-time configurable structure is disclosed. Such a method includes, in one embodiment receiving a description of circuit functionality from a user for implementation in the one-time configurable device, where the functionality includes a portion that is designated by the user to be reconfigurable. A method in accordance with an embodiment of the invention then models a reconfigurable structure that has enough capacity to accommodate the designated functionality. Optionally, some embodiments of the invention add in more capacity than is required to implement the designated functionality to allow for future reprogramming. The method then embeds the reconfigurable structure in the one-time configurable device. In certain embodiments, the one-time configurable device can be a mask-programmed MBA, gate array, or standard cell, while the reconfigurable structure is a PLA or modified PLA.Type: GrantFiled: June 8, 2001Date of Patent: July 27, 2004Assignee: Lightspeed Semiconductor CorporationInventors: Robert Osann, Jr., Shafy Eltoukhy, Shridhar Mukund, Lyle Smith
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Patent number: 6696856Abstract: Described herein is an ASIC having an array of predesigned function blocks. The function blocks can be used to implement combinational logic, sequential logic, or a combination of both. The function blocks also have a selectable output drive strength. The output drive strength can be selected, in some embodiments, using mask programming.Type: GrantFiled: October 30, 2001Date of Patent: February 24, 2004Assignee: Lightspeed Semiconductor CorporationInventors: Lyle Smith, Eric Dellinger, Eric West, Shridhar Mukund
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Patent number: 6694491Abstract: In accordance with the invention, a method for customizing a one-time configurable integrated circuit to include a multi-time configurable structure is disclosed. Such a method includes, in one embodiment receiving a description of circuit functionality from a user for implementation in the one-time configurable device, where the functionality includes a portion that is designated by the user to be reconfigurable. A method in accordance with an embodiment of the invention then models a reconfigurable structure that has enough capacity to accommodate the designated functionality. Optionally, some embodiments of the invention add in more capacity than is required to implement the designated functionality to allow for future reprogramming. The method then embeds the reconfigurable structure in the one-time configurable device. In certain embodiments, the one-time configurable device can be a mask-programmed MBA, gate array, or standard cell, while the reconfigurable structure is a PLA or modified PLA.Type: GrantFiled: February 25, 2000Date of Patent: February 17, 2004Assignee: Lightspeed Semiconductor CorporationInventors: Robert Osann, Jr., Shafy Eltoukhy, Shridhar Mukund, Lyle Smith
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Patent number: 6690194Abstract: A gate array in accordance with the invention includes a matrix of function blocks capable of being configured to implement combinational, sequential, and memory modes of operation, as well as providing tri-state drivers and buffers in useful numbers. The function block includes a logic circuit with a first bit storage unit, which is selectively configurable to behave as combinational logic or to store a first bit, and a second bit storage unit, which is also selectively configurable to behave as combinational logic or to store a second bit. The matrix of function blocks in accordance with the invention is also useful to properly distribute clocks throughout the gate array.Type: GrantFiled: October 7, 1999Date of Patent: February 10, 2004Assignee: Lightspeed Semiconductor CorporationInventors: Dana How, Adi Srinivasan, Abbas El Gamal
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Patent number: 6680626Abstract: A differential receiver having a pair of cross-coupled signal conditioning devices improves transition time and data signal integrity. In an embodiment, the differential receiver includes two signal input nodes and a plurality of transistors, and two signal output nodes. The pair of cross-coupled signal conditioning devices are coupled to the transistors and function to reduce voltage swing between the two output nodes, thereby keeping the transistors in a saturation region.Type: GrantFiled: June 5, 2002Date of Patent: January 20, 2004Assignee: Lightspeed Semiconductor CorporationInventors: Chit-Ah Mak, Bingda B. Wang, Eric West, Robert A. Olah
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Publication number: 20030212979Abstract: A programmable logic array (PLA) in accordance with the invention achieves a maximum amount of depopulation of programmable connections while still implementing a logic function and maintaining flexibility for future reprogramming. In addition, a PLA in accordance with the invention can be built so that no matter what functionality is programmed, performance characteristics for the device are maintained. Further, a PLA in accordance with the invention does not require a regular array structure.Type: ApplicationFiled: June 10, 2003Publication date: November 13, 2003Applicant: Lightspeed Semiconductor CorporationInventors: Robert Osann, Patrick Hallinan, Jung Lee, Shridhar Mukund
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Patent number: 6613611Abstract: A customizable ASIC routing architecture is provided. The architecture utilizes the uppermost metal layers of an ASIC composed of an array of function blocks for routing among function blocks while lower layers are used for local interconnections within the function blocks. The second-to-uppermost metal layer is fixed and generally includes a plurality of parallel segmented conductors extending in a first direction. The uppermost metal layer is customizable in a predesignated manner. Metal in the uppermost metal layer is selectively placed in tracks, which are substantially perpendicular to the segmented conductors in the layer below. Vias are provided between the two uppermost layers. One embodiment of the invention permits one-mask customization of an ASIC. Other embodiments allow a determination to be made of the ideal number of custom mask steps, taking into consideration performance, cost, time, and routability.Type: GrantFiled: December 22, 2000Date of Patent: September 2, 2003Assignee: Lightspeed Semiconductor CorporationInventors: Dana How, Robert Osann, Jr., Eric Dellinger
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Patent number: 6611932Abstract: A system for testing an integrated circuit, and particularly a gate array, is disclosed which includes, prior to coupling the array to form a user-designed circuit, predesigned logic that enables testing of the user-designed circuit. The predesigned logic allows logic blocks in the array to operate in “freeze” mode or to operate in normal mode, where normal mode is defined by the user-designed circuit. When the logic blocks are selected to be frozen, the logic blocks behave as a series of daisy-chained master-slave flip-flops. In normal mode, a logic block can implement combinational, sequential, or other functions and still later be as a master-slave flip-flop. Moreover, each logic block is further equipped for addressable mode control, allowing selected logic blocks to be exercised in isolation once stimulus data is shifted in, simplifying test generation and improving fault coverage.Type: GrantFiled: January 24, 2002Date of Patent: August 26, 2003Assignee: LightSpeed Semiconductor CorporationInventors: Dana How, Adi Srinivasan, Robert Osann, Jr., Shridhar Mukund
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Patent number: 6498361Abstract: On a wafer that includes multiple distinct designs in each die region, a memory is included in each die region. The memory stores information specific to the design implemented in the same die region. Such stored information may include a circuit design identifier or a proprietary technology identifier. Such identifiers minimize IC confusion and aid in tracking usage of proprietary technology.Type: GrantFiled: August 26, 1998Date of Patent: December 24, 2002Assignee: Lightspeed Semiconductor CorporationInventor: Robert Osann, Jr.
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Publication number: 20020073369Abstract: A system for testing an integrated circuit, and particularly a gate array, is disclosed which includes, prior to coupling the array to form a user-designed circuit, predesigned logic that enables testing of the user-designed circuit. The predesigned logic allows logic blocks in the array to operate in “freeze” mode or to operate in normal mode, where normal mode is defined by the user-designed circuit. When the logic blocks are selected to be frozen, the logic blocks behave as a series of daisy-chained master-slave flip-flops. In normal mode, a logic block can implement combinational, sequential, or other functions and still later be as a master-slave flip-flop. Moreover, each logic block is further equipped for addressable mode control, allowing selected logic blocks to be exercised in isolation once stimulus data is shifted in, simplifying test generation and improving fault coverage.Type: ApplicationFiled: January 24, 2002Publication date: June 13, 2002Applicant: LightSpeed Semiconductor CorporationInventors: Dana How, Adi Srinivasan, Robert Osann, Shridhar Mukund
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Patent number: 6399400Abstract: A gate array integrated circuit wafer is formed having M−N generic metal interconnection layers and having performance and/or electrical testing circuits which are operative using only the M−N generic metal interconnection layers. Performance and/or electrical tests are performed after generic fabrication is completed, but before the final customization of the wafers. Wafers are sorted and assigned to performance and/or yield bins based upon the results of the performance and/or electrical tests. In another embodiment, all M layers are deposited prior to performance and/or electrical testing; however, the Mth layer is not etched within the active die area prior to performance and/or electrical testing. Subsequent to binning based upon the test results, the final customization is performed by etching the Mth metal layer.Type: GrantFiled: March 19, 1999Date of Patent: June 4, 2002Assignee: LightSpeed Semiconductor CorporationInventors: Robert Osann, Jr., Shafy Eltoukhy
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Patent number: 6223313Abstract: A system for testing an integrated circuit, and particularly a gate array, is disclosed which includes, prior to coupling the array to form a user-designed circuit, predesigned logic that enables testing of the user-designed circuit. The predesigned logic allows logic blocks in the array to operate in “freeze” mode or to operate in normal mode, where normal mode is defined by the user-designed circuit. Much of the same circuitry in the logic blocks is, in fact, used in both modes of operation, thus minimizing circuitry added due to test. When the logic blocks are selected to be frozen, the logic blocks behave as a series of daisy-chained master-slave flip-flops. Stimulus data is shifted into the array and captured data is shifted out of the array through the daisy-chained flip-flops.Type: GrantFiled: December 5, 1997Date of Patent: April 24, 2001Assignee: LightSpeed Semiconductor CorporationInventors: Dana How, Adi Srinivasan, Robert Osann, Shridhar Mukund
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Patent number: 6133582Abstract: A gate array integrated circuit wafer is formed having M-N generic metal interconnection layers and having performance and/or electrical testing circuits which are operative using only the M-N generic metal interconnection layers. The performance and electrical testing circuits are located in the active chip area and/or in the scribe line area between dies on the wafer. Performance and/or electrical tests are performed after generic fabrication is completed, but before the final customization of the wafers. Wafers are sorted and assigned to performance and/or yield bins based upon the results of the performance and/or electrical tests. The contents of different bins are provided to different customers for addition of the final N application specific metal interconnection layers based upon the customer's performance and/or yield requirements.Type: GrantFiled: May 14, 1998Date of Patent: October 17, 2000Assignee: Lightspeed Semiconductor CorporationInventors: Robert Osann, Jr., Shafy Eltoukhy
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Patent number: 6014038Abstract: A gate array in accordance with the invention includes a matrix of function blocks capable of being configured to implement combinational, sequential, and memory modes of operation, as well as providing tri-state drivers and buffers in useful numbers. The function block includes a logic circuit with a first bit storage unit, which is selectively configurable to behave as combinational logic or to store a first bit, and a second bit storage unit, which is also selectively configurable to behave as combinational logic or to store a second bit. The matrix of function blocks in accordance with the invention is also useful to properly distribute clocks throughout the gate array.Type: GrantFiled: March 21, 1997Date of Patent: January 11, 2000Assignee: LightSpeed Semiconductor CorporationInventors: Dana How, Adi Srinivasan, Abbas El Gamal