Abstract: A clock data recovery circuit includes a binary phase detector configured to receive an incoming data signal and a recovered clock, and output a phase offset signal and recovered data; a digital loop control circuit configured to receive the phase offset signal and output a control signal; and a digital frequency generator configured to receive the control signal and output the recovered clock. A method of clock recovery includes generating a digital phase offset signal from incoming data and feedback clock signals; generating a clock frequency control signal from the phase offset signal; generating a recovered clock in response to the control signal; slowing down the recovered clock when the digital phase offset signal has a first binary state; speeding up the recovered clock when the digital phase offset signal has a second binary state; and holding the recovered clock when the digital phase offset signal has a third binary state.

Abstract: An open loop clock divider circuit includes (a) a first divider configured to receive an incoming clock signal and output a first divided clock signal, (b) a flying-adder synthesizer configured to fractionally divide the first divided clock signal and output a fractionally divided clock signal, and (c) a second divider configured to receive the fractionally divided clock signal and output a second divided clock signal. The open loop clock divider circuit advantageously provides a fractional divider in which there is no feedback loop between the source frequency (fs) and the destination frequency (fd). Methods of generating a divided clock signal involving the open loop clock divider circuit are also disclosed.