Abstract: An integrated transistor device operates with a linear triode vacuum tube like characteristic with a very low output impedance and a large interaction between the gate and drain potentials. The drain current of a first transistor is connected directly to the source of a second transistor which has a low input impedance matching the output impedance of the first transistor. The gate of the second transistor is held at a positive potential and functions to provide isolation of the varying drain signal from the drain of the first transistor and to provide a high impedance at the output terminal. This device structure provides high input impedance, high current gain, high output impedance and a linear operating characteristic.

Abstract: Disclosed is an integrated transistor structure having increased conductance and operating speed including a complementary insulated gate field-effect transistor pair, each including a source and drain region with a gate contact positioned therebetween, an ohmic contact to the source regions, and a Schottky contact to each of the drain regions. The dopant concentration of the drain regions is sufficiently low to prevent the Schottky contact from forming an ohmic contact with the drain regions. The gates of the two transistors are interconnected and function as the input terminal, and the two Schottky contacts are interconnected as the output of the device. The operation of the device is such that the lightly-doped drain regions act as bases of bipolar transistors, with the emitters formed by the Schottky diodes.

Abstract: A CMOS analog to digital flash converter cell includes an input for receiving an analog signal to be converted to a digital value, a predetermined connection to a resistance ladder for providing a reference voltage, an output, CMOS comparator/inverter stage having drain connections commonly connected to the output, a level shift capacitor connected to input gate connections of the comparator/inverter stage, and three bi-phase clocked CMOS switches: a first switch for connecting the reference voltage to one side of the level shift capacitor during a first phase of a clock period; a second switch for connecting the output to the input gate connections on the other side of the level shift capacitor during the first phase of the clock period, and a third switch for connecting the input voltage to the one side of the level shift capacitor during a second phase of the clock period.