Abstract: A target amplitude for an acquisition gain-loop is determined. A tracking gain-loop is configured to adjust a gain of the tracking gain-loop during a data portion of the received signal, wherein the received signal comprises an acquisition portion and the data portion. An acquisition gain-loop is configured to adjust a gain of the acquisition gain-loop during the acquisition portion of the received signal. A detector is configured to detect in the data portion an occurrence of a pattern identical to a portion of the acquisition portion. An amplitude estimation block is configured to compute an amplitude estimate based at least in part on the detected portion. A target amplitude updating block is configured to update the target amplitude based at least in part on the amplitude estimate.

Abstract: Offset is canceled by determining a voltage level to set a body input of a transistor to. The body input of the transistor is set to the determined voltage level to cancel offset associated with the transistor.

Abstract: A NAND Flash memory controller is used to perform an erase operation on a NAND Flash memory chip including to a cell on the NAND Flash memory chip; the cell is configured to store a first number of bits. It is determined whether the erase operation performed on the NAND Flash memory chip is successful. In the event it is determined that the erase operation performed on the NAND Flash memory chip is unsuccessful, the number of bits stored by the cell is reduced from the first number of bits to a second number of bits; the second number of bits is strictly less than the first number of bits.

Abstract: A defect portion in a signal is processed by receiving an input signal. A location of a defect portion within the input signal and an amplitude of the defect portion is determined. An adjusted signal is generated by adjusting the amplitude of the defect portion using the determined location of the defect portion and the determined amplitude of the defect portion. Information associated with the adjusted signal is decoded.

Abstract: A signal is encoded by receiving input data. A first portion of the input data is encoded to obtain a first set of encoded data. At least some part of the input data is processed to determine which one of a plurality of subsets the input data corresponds to. In the event the input data corresponds to a first subset having a greater signal margin (SM) than a second subset, the first set of encoded data and a second portion of the input data are output. In the event the input data corresponds to the second subset, the second portion of the input data is encoded to obtain a second set of encoded data and the first set of encoded data and the second set of encoded data are output.

Abstract: Outputting information for recovering a sequence of data is disclosed. Outputting includes making a decision that selects a first sequence of states corresponding to a surviving path, determining a second sequence of states corresponding to a non-surviving path associated with the decision, and defining a possible error event based at least in part on the second sequence of states.

Abstract: An offset compensation scheme using a digital-to-analog converter (DAC) is disclosed. In some embodiments, a DAC is coupled to a circuit having an undesired current or voltage offset and is configured to at least in part compensate for the undesired current or voltage offset. For example, in some embodiments, the DAC injects current or voltage into the circuit that shifts a current or voltage of the circuit by an amount equal or similar in magnitude but opposite in polarity to a shift in the current or voltage of the circuit caused by the undesired current or voltage offset.

Abstract: A complementary error evaluator polynomial is generated by obtaining a syndrome polynomial and one or more erasure locations. The syndrome polynomial and the erasure locations are associated with Reed-Solomon encoded information. A complementary error evaluator polynomial and an error locator polynomial are simultaneously generated using the syndrome polynomial and the erasure locations where the complementary error evaluator polynomial is a complement of the error evaluator polynomial.

Abstract: A length of a separator to be skipped on the storage disk is compared with a threshold. The threshold is associated with a maximum value for which a timing loop is able to be paused without causing the timing loop to have inaccurate timing. If the length is greater than the threshold, a first split sector format is assigned to the split sector and that information is recorded. In such cases, a first portion and a second portion both include synchronization information. If the length is less than the threshold, a second split sector format is assigned to the split sector and that information is recorded. In such cases, the first portion includes synchronization information and the second portion of the split sector excludes synchronization information.

Abstract: Binary Bose-Chaudhuri-Hocquenghem (BCH) encoded data is processed by obtaining a set of syndromes associated with the binary BCH encoded data, including a subset of odd-term syndromes and a subset of even-term syndromes. During initialization of a variant error-locator polynomial, {circumflex over (?)}(x), the subset of even-term syndromes, but not the subset of odd-term syndromes, are loaded into the variant error-locator polynomial, {circumflex over (?)}(0)(x).

Abstract: Processing polynomials is disclosed. At least a portion of processing associated with an error evaluator polynomial and at least a portion of processing associated with an error locator polynomial are performed simultaneously. The error evaluator polynomial and the error locator polynomial are associated with Berlekamp-Massey processing. Data associated with the error evaluator polynomial is removed, including by shifting data in an array so that at least one element in the array is emptied in a shift.

Abstract: A probability is determined, including by obtaining a set of probability ratios, wherein each probability ratio in the set is a ratio of a first probability to a second probability. A probability P(Em=z) that an mth error symbol Em has a level of z is determining based at least in part on one or more dominant error patterns.

Abstract: A technique for decoding information, including a Viterbi decoder configured to decode (1) Front-end processed ADC data and (2) an output of an iterative error correction decoder in the event error correction decoding fails. The iterative error correction decoder is configured to decode Viterbi decoded data generated by the Viterbi decoder.

Abstract: A clock is adjusted by obtaining a first plurality of samples and a second plurality of samples associated with a preamble portion of a data packet. The first plurality of samples and the second plurality of samples are sampled using a clock. A first intermediate value is determined based at least in part on the first plurality of samples and a second intermediate value is determined based at least in part on the second plurality of samples. An ending value associated with an end of the preamble portion is determined based at least in part on the first intermediate value and the second intermediate value. The clock is adjusted based at least in part on the ending value without use of a second order timing loop.

Abstract: RLL encoding is performed to generate RLL data, including by: using a first run-length constraint and using a second run-length constraint. G is a maximum number of zeroes between two ones, I is a maximum number of zeroes between two ones in either a first subsequence or a second subsequence where the first subsequence includes odd bits associated with a DC-balanced sequence and the second subsequence includes even bits associated with the DC-balanced sequence, and S is a number of bits per symbol associated with a systematic ECC. The RLL data is encoded using the systematic ECC to obtain ECC data which includes one or more data symbols and one or more parity symbols. The data symbols and the parity symbols are interleaved.

Abstract: A system for controlling a dynamic range of an analog to digital converter (ADC) signal is disclosed. The system includes an ADC configured to receive an ADC input signal and output ADC samples; an error computation block coupled to the output of the ADC and configured to compute an error based at least in part on a target and the ADC samples, wherein the target has a constraint that is indicative of a desired dynamic range of the ADC input signal; and an analog front end coupled to the input of the ADC, wherein the analog front end comprises a variable gain amplifier whose gain is adjusted based at least in part on the error.

Abstract: Recovering a data signal is disclosed. Recovering includes receiving an input signal from a magnetic recording channel, sampling the input signal according to a sampling clock having a sampling phase wherein the sampling phase is determined at least in part by comparing the sampled input signal to a signal associated with a decision, and filtering the sampled input signal according to a target.

Abstract: Data is processed by obtaining data and redundant information from an expected position in a channel. Soft position information associated with the data is obtained and error correction decoding is performed using the data, the redundant information, and the soft position information to obtain a decoded position and decoded data. It is determined if the decoded position matches the expected position and the decoded data is output in the event the decoded position matches the expected position.

Abstract: Processing a sequence of data frames in an error correction code (ECC) decoder is disclosed. Processing includes receiving a first data frame in the sequence of data frames, storing the first data frame, initiating processing of the first data frame using the ECC decoder that includes a faster stage and a slower stage, receiving a second data frame from the input sequence of data frames, storing the second data frame, and initiating processing of the second data frame through the ECC decoder before the first data frame is finished being processed using the ECC decoder.

Abstract: Detecting a defect on a storage device is disclosed. Detecting includes receiving a signal read from a storage device, sampling the signal to obtain a set of signal samples, wherein the sampling starts at an arbitrary time, computing a defect value for a defect type using the set of signal samples, comparing the defect value with a threshold associated with the defect type, determining whether there is a defect of the defect type based at least in part on the comparison, and in the event that a defect is detected, outputting an indication associated with the defect.