Abstract: In a bus type LAN, the data transmitted from a terminal (14) is detected by an adapter (1) connected to one end of a bus (3), and in response thereto the adapter (1) transmits a pulse signal onto the bus (3). An adapter (2) connected to the other end of the bus (3) receives the data transmitted from the terminal (14) and detects its source terminal address. A difference in time between the arrival of the data from the terminal (14) and the arrival of the pulse signal from the adapter (1) is measured by a counter circuit (21), and the count value obtained is stored in a memory (23), forming a pair with the corresponding source terminal address. Thus, the count value can be obtained for each terminal during the normal operation of the LAN. The data of the memory (23) are extracted by a personal computer (5), where the physical position of each terminal is calculated in accordance with the bus propagation velocity, and is displayed or printed out as a physical constitution diagram.
Type:
Grant
Filed:
March 12, 1997
Date of Patent:
September 19, 2000
Assignees:
Hitachi Electronics Services Co, Ltd, Link Laboratory Inc.
Abstract: A switching system exchanges communication information as fixed length cells between a plurality of incoming and outgoing highways. The fixed length cells each have a plurality of data portions with one data portion designated as a header portion for containing switching information. An address generating circuit generates read addresses and write addresses in response to the header portion of each cell and a control circuit. The plurality of cells from the incoming highways are simultaneously rotated in a rotation matrix with each of the cell's data portions rotated to a unique internal path. The data portions are then transmitted to identical write addresses in a plurality of memories via delay circuitry. The write addresses are transmitted through shift registers to the plurality of memories to allow the data portions of a single cell to occupy identical addresses within a plurality of memories.
Type:
Grant
Filed:
May 21, 1990
Date of Patent:
February 2, 1993
Assignees:
Hitachi, Ltd., Hitachi VLSI Engineering Corporation, Link Laboratory Inc.
Abstract: A fixed-length packet switching system, in which fixed-length packets (cells) each composed of a header portion and a data portion are received from a plurality of input lines, and after conversion of the header portions, the received packets are transmitted onto selected ones of output lines designated by their header portions.