Abstract: A computer system may include a chassis defining a front and a rear. The chassis may include a vertically oriented midplane disposed therein, the midplane including a plurality of front module slots for receiving front electronic modules from the front of the chassis, and a plurality of rear module slots for receiving rear electronic modules from the rear of the chassis. A cooling system may be provided within the chassis and may generate an upwardly-directed front air flow within the chassis directed at selected ones of the front electronic modules and an upwardly-directed rear air flow within the chassis directed at selected ones of the rear electronic modules. The front air flow is separate from and independent of the rear air flow. The selected front and rear electronic modules may be disposed in the chassis so as to separate the front air flow into a plurality of substantially equal front air streams and the rear air flow into a plurality of substantially equal rear air streams, respectively.

Abstract: Embodiments of the present invention include enhanced functionalities and components within a Communication Endpoint Processor (CEP) that act as an interface between computational and communications domains. The embodiments disclosed herein deliver a complete memory mapped high performance interface that has the ability to support the simultaneous transmission of multiple frames of multiple sizes, and that has the ability to interrupt the transmission of lower priority frames in order to send higher priority frames.

Abstract: Embodiments of the present invention include enhanced functionalities and components within a Communication Endpoint Processor (CEP) that act as an interface between computational and communications domains. The embodiments disclosed herein deliver a complete memory mapped high performance interface that has the ability to support the simultaneous transmission of multiple frames of multiple sizes, and that has the ability to interrupt the transmission of lower priority frames in order to send higher priority frames.

Abstract: A computer system may include a chassis defining a front and a rear. The chassis may include a vertically oriented midplane disposed therein, the midplane including a plurality of front module slots for receiving front electronic modules from the front of the chassis, and a plurality of rear module slots for receiving rear electronic modules from the rear of the chassis. A cooling system may be provided within the chassis and may generate an upwardly-directed front air flow within the chassis directed at selected ones of the front electronic modules and an upwardly-directed rear air flow within the chassis directed at selected ones of the rear electronic modules. The front air flow is separate from and independent of the rear air flow. The selected front and rear electronic modules may be disposed in the chassis so as to separate the front air flow into a plurality of substantially equal front air streams and the rear air flow into a plurality of substantially equal rear air streams, respectively.

Abstract: An embodiment of one of the inventions disclosed herein is a computer system that includes a plurality of interconnected computational hosts, each of which are connected to one of a plurality of buffers. Each of the buffers includes a plurality of buffer spaces. Each of the computational hosts may be configured such that each transfer of a data packet from one of the plurality of computational hosts acting as a source of the data packet to another one of the plurality of computational hosts acting as a destination of the data packet is controlled by an availability of buffer spaces in the buffer coupled to the destination computational host.

Abstract: In a multi-processor system with a high degree of inter processor communication, an operating system extension is described as a kernel function to poll a receive buffer. This is an opportunistic poll that continues to run in the user context after an application process has invoked the kernel with a blocking receive function. It is also running whenever no higher priority task is running. New data packets may be received for the present user application process while avoiding context switches, and for a different user process while avoiding interrupts. A hardware implemented delay timer and a buffer fill monitor generate interrupts when the system is not polling, thus guaranteeing a maximum latency and preventing buffer overflow, but these interrupts are largely avoided by polling when the system is handling a large amount of inter processor data traffic.

Abstract: A computer system may include a chassis defining a front and a rear. The chassis may include a vertically oriented midplane disposed therein, the midplane including a plurality of front module slots for receiving front electronic modules from the front of the chassis, and a plurality of rear module slots for receiving rear electronic modules from the rear of the chassis. A cooling system may be provided within the chassis and may generate an upwardly-directed front air flow within the chassis directed at selected ones of the front electronic modules and an upwardly-directed rear air flow within the chassis directed at selected ones of the rear electronic modules. The front air flow is separate from and independent of the rear air flow. The selected front and rear electronic modules may be disposed in the chassis so as to separate the front air flow into a plurality of substantially equal front air streams and the rear air flow into a plurality of substantially equal rear air streams, respectively.

Abstract: A system and method allows a virtual server to be assigned to any of a plurality of physical computes hosts in a networked computing system. Each physical compute host includes a motherboard and a secure management controller that includes a secure memory vault for storing virtual server secure profile data and a BIOS switch for loading a BIOS memory with a BIOS image from the secure memory and controlling access to the BIOS memory by the motherboard. The virtual server secure profile data is transmitted to the secure memory under the exclusive control of a secure infrastructure layer including a common system controller a secure network that is distinct from the network over which the operating system and application stack is loaded.

Abstract: A high performance network adapter is provided for forwarding traffic and providing adaptation between packetized memory fragment based processor links of multiple CPUs and multiple switch planes of a packet switching network. Low latency for short and long packets is provided by innovative packet reassembly, overlapping transmission, and reverse order transmission in the upstream direction, and cut through operation in the downstream direction.

Abstract: In a networked multi computer environment, with redundant links, network interface cards (NICs) are commonly duplicated and teamed to provide a recovery mechanism when network components fail. Embodiments of the present inventions avoid teaming of pairs of NICs and provide a computing host with redundant network connections for the computing host through a switch that is transparent to the computing host. The computing host itself; that is, its hardware and software, is relieved of the duty of network access redundancy and returned to the simple, simplex networking operating mode. The switch replaces a potentially large number of NICs and the need for computing host network access redundancy management which leads to hardware and software cost reductions and increases the robustness and reliability of the system through redundant network access.

Abstract: A reliable method for inter-computer packet transport in multi-process and multi-computer environments includes acknowledgments of received packets. To enhance the reliability and fast recovery of lost packets, a bit-mapped message is used for selective acknowledgments by which individual messages may be selected for retransmission. Further functionalities cover the cases where packets may have been received out-of-order, or an acknowledgment was lost.

Abstract: A high performance network adapter is provided for forwarding traffic and providing adaptation between packetized memory fragment based processor links of multiple CPUs and multiple switch planes of a packet switching network. Low latency for short and long packets is provided by innovative packet reassembly, overlapping transmission, and reverse order transmission in the upstream direction, and cut through operation in the downstream direction.

Abstract: In a multi-processor system with a high degree of inter processor communication, an operating system extension is described as a kernel function to poll a receive buffer. This is an opportunistic poll that continues to run in the user context after an application process has invoked the kernel with a blocking receive function. It is also running whenever no higher priority task is running. New data packets may be received for the present user application process while avoiding context switches, and for a different user process while avoiding interrupts. A hardware implemented delay timer and a buffer fill monitor generate interrupts when the system is not polling, thus guaranteeing a maximum latency and preventing buffer overflow, but these interrupts are largely avoided by polling when the system is handling a large amount of inter processor data traffic.

Abstract: A multilayer midplane board has a front side and a back side and includes a first partially plated through-hole; a second partially plated through-hole spaced away from the first partially plated through-hole, and a first conductive signal track that electrically couples a selected plated section of the first partially plated through-hole directly adjacent the front side to a selected plated section of the second partially plated through-hole adjacent the back side.

Abstract: A protocol element referred to as a secure handle is described which provides an efficient and reliable method for application-to-application signaling in multi-process and multi-computer environments. The secure handle includes an absolute memory reference which allows the kernel to more quickly and efficiently associate a network data packet with an application's communication context in the kernel.

Abstract: A protocol suite for inter-process communication in multi-process and multi-computer environments is described which supports one or more loosely flow-controlled connections to be established over a tightly flow-controlled connection. The tightly flow-controlled connections between processes provide a reliable underlying network between the members of a multiprocessing environment over which multi-computer applications can then efficiently communicate by setting up loosely flow-controlled connections.

Abstract: An embodiment of one of the inventions disclosed herein is a computer system that includes a plurality of interconnected computational hosts, each of which are connected to one of a plurality of buffers. Each of the buffers includes a plurality of buffer spaces. Each of the computational hosts may be configured such that each transfer of a data packet from one of the plurality of computational hosts acting as a source of the data packet to another one of the plurality of computational hosts acting as a destination of the data packet is controlled by an availability of buffer spaces in the buffer coupled to the destination computational host.

Abstract: A reliable method for inter-computer packet transport in multi-process and multi-computer environments includes acknowledgments of received packets. To enhance the reliability and fast recovery of lost packets, a bit-mapped message is used for selective acknowledgments by which individual messages may be selected for retransmission. Further functionalities cover the cases where packets may have been received out-of-order, or an acknowledgment was lost.

Abstract: Embodiments of the present invention include enhanced functionalities and components within a Communication Endpoint Processor (CEP) that act as an interface between computational and communications domains. The embodiments disclosed herein deliver a complete memory mapped high performance interface that has the ability to support the simultaneous transmission of multiple frames of multiple sizes, and that has the ability to interrupt the transmission of lower priority frames in order to send higher priority frames.

Abstract: Embodiments of the present invention define a modular architecture that provides the physical level of interconnect that is used to cost effectively deploy high performance and high flexibility communication networks. Aspects of the physical communications are described to deliver scalable computer to computer communications as well as scalable computer to I/O communications, scalable I/O to I/O communications, and scalable function to function communications with a low cable count. Embodiments of the present invention focus on the physical switched communications layer, as the interconnect physical layer, functions, chassis; modules have been designed as an integrated solution.