Abstract: The wiring length measurement apparatus includes a distance calculation unit, by using a plurality of coordinates of bending points and a wiring width of CAD data of a high-density wiring including a meander wiring, seeking each endpoint that exists on an edge in a wiring width direction and is a flexion point of each inner circuit side, and calculating distances between each adjacent endpoint and a measurement unit measuring a wiring length of the high-density wiring by calculating a sum of the distances between each endpoint calculated by the distance calculation unit.

Abstract: An illumination device includes a metal base substrate in a flat planar shape, a plurality of LED modules, and a driving unit which drives each of the LEDs arranged on the metal base substrate. The LED modules have an organic substrate, a plurality of LEDs which are arranged on the organic substrate, a metal member, LED control signal terminals which are set on the edge of the organic substrate, and voltage feed terminals which are set on the edge of the organic substrate. The metal member corresponds to each LED and to which the heat from the LEDs is conducted, and which is electrically connected via a switch element from an electrode of the LED, and which penetrates the organic substrate toward its width direction from the LED mounting surface of the organic substrate and is exposed from the opposite surface.

Abstract: The invention includes one or more LED elements, a silicon substrate on which the LED elements are mounted via micro bumps and internally formed wiring is connected to the micro bumps, a heat insulation organic substrate which is stuck to the opposite side of the LED elements-mounting side of the silicon substrate and has through-holes in which the wiring goes through, a chip-mounting substrate which is stuck to the opposite side of the silicon substrate side of the heat insulation organic substrate and internally formed wiring is connected to wiring in the through-holes of the heat insulation organic substrate, and an LED control circuit chip which is connected to the wiring of the chip-mounting substrate via micro bumps, and mounted via the micro bumps on the opposite side of the heat insulation organic substrate side of the chip-mounting substrate.

Abstract: The invention includes one or more LED elements, a silicon substrate on which the LED elements are mounted via micro bumps and internally formed wiring is connected to the micro bumps, a heat insulation organic substrate which is stuck to the opposite side of the LED elements-mounting side of the silicon substrate and has through-holes in which the wiring goes through, a chip-mounting substrate which is stuck to the opposite side of the silicon substrate side of the heat insulation organic substrate and internally formed wiring is connected to wiring in the through-holes of the heat insulation organic substrate, and an LED control circuit chip which is connected to the wiring of the chip-mounting substrate via micro bumps, and mounted via the micro bumps on the opposite side of the heat insulation organic substrate side of the chip-mounting substrate.

Abstract: A semiconductor device includes an Si substrate having a first surface provided with semiconductor elements, such as a CMOS transistor and a diode, and a second surface opposite to the first surface. On one of the first and the second surfaces, a bypass capacitor is formed. The bypass capacitor includes a Vcc power supply layer and a GND layer which serve to supply a power supply voltage to the semiconductor element, and a high dielectric constant layer sandwiched between the Vcc power supply layer and the GND layer.

Abstract: A BSC macrostructure for three-dimensional wiring includes a BSC (boundary scan cell) and an aperture electrode for electrode connection which is connected to the BSC.

Abstract: A wiring structure of a substrate adapted to mount a plurality of integrated circuits has a signal wire for connecting the integrated circuits to each other, first and second power supply layers faced to each other, and return path wires arranged generally in parallel to the signal wire. One of the return path wires has opposite terminal ends connected to the first power supply layer (Vcc layer). The other return path wire has opposite terminal ends connected to the second power supply layer (GND layer).

Abstract: To provide a semiconductor chip whose number of electrodes are minimized while the horizontal position between the semiconductor chip and the mounted substrate is maintained in implementation to avoid any connection problem, as well as to prevent the damage to the semiconductor circuit of such chip. For example, there is a cross-shaped connection bump disposition area which is formed by memory banks which face with each other with a certain distance. And in the area in the cross-shaped connection bump disposition area, signal input output connection bumps (the first electrodes) are disposed and form a group.

Abstract: The semiconductor memory device proposed in the present invention comprises the buffer control circuit which, when writing the data, controls the data input buffer so that the data from the same timing as the clock when the writing command is input is written in the activated memory bank, and which, when reading the data, controls the data output buffer so that the data with the read latency of more than 3 clock cycles after when the reading command is input is read from the activated memory bank.

Abstract: The semiconductor memory device proposed in the present invention comprises memory cells disposed in the row direction and the column direction, a plurality of first lines by which supply voltages are supplied in order to select memory cells disposed in the row direction among the plurality of cells, a plurality of second lines by which supply voltages are supplied in order to select memory cells disposed in the column direction among the plurality of cells, the data lines which input and output the data to the selected memory cells, the first power voltage supply circuit which supplies the predetermined supply voltages to the first lines corresponding with the externally input row address synchronizing with an act command, and the second power voltage supply circuit which supplies the predetermined supply voltages to the second lines corresponding with the externally input column address synchronizing with an act command.