Abstract: The invention combines the repeater functions outlined in the IEEE 802.3 Standards, §27, and the 100BASE-TX PCS and PMA. The disclosed FEMR provides four ports in the PQFR packet of its 100 pins. Such extension ports allow multiple serial connections of the FEMR's, increasing the number of all ports on the repeaters. Therefore, the price of each repeater can be reduced to its minimum, and the serial device does not need an external logic circuit. Additionally, the serial device also supports the extension among built-in inter-repeaters used in stackable backplanes.

Abstract: The invention combines the repeater functions outlined in the IEEE 802.3 Standards, §27, and the 100BASE-TX PCS and PMA. The disclosed FEMR provides four ports in the PQFR packet of its 100 pins. Such extension ports allow multiple serial connections of the FEMR's, increasing the number of all ports on the repeaters. Therefore, the price of each repeater can be reduced to its minimum, and the serial device does not need an external logic circuit. Additionally, the serial device also supports the extension among built-in inter-repeaters used in stackable backplanes.

Abstract: A parallel signal processing device for high speed timing recovery in a high speed transfer network includes a plurality of data sampling processors (DSP), a central phase-error processor (CPP), and a recovered clock phase adjuster (RCPA. The sampling of transfer data, processing of sampling data, and adjustment of the recovered clock are executed by a plurality of data sampling processors for producing phase difference signals which are then transferred separately to a central phase-error processor. Phase-error adjustment signals for each data sampling processor are produced by the central phase-error processor, and the recovered clock phase for each data sampling processor is adjusted by the recovered clock phase adjuster according to the phase-error.

Abstract: A multiple rate waveshaping method and apparatus for converting transmission data into communications code synthesized waveforms having different protocol frequencies in the physical layer of the fast Ethernet utilizes two state machines which convert the transmission data into appropriate waveforms using predetermined wave shaping signals, the outputs of the state machines being multiplexed and transmitted over the Ethernet media using a common set of differential current sourced drivers.

Abstract: A digital phase-locked loop adjusts the phase of a Recovered Clock in the receiver under the condition of asynchronous serial data transmission so that the phases of the transmission data are locked in order to reduce errors in read data. The digital phase-locked loop includes a zero-phase start circuit, a phase-error detecting circuit, an error-filtering circuit, a Recovered Clock adjusting circuit and a clock-generation circuit. This phase-locked loop generates a set of clocks through the detection of the transmission data level in the zero-phase start circuit so as to lock the phase of the transmission data quickly, and the phase-error detecting circuit detects the phase error between the phase of the transmission data and the phase of the Recovered Clock, after which the phase error signal is filtered through the adaptive filtering circuit for conversion into error-adjusting signals.