Abstract: An apparatus architecture is provided which permits an easily programmed apparatus (10) to serve as an equivalent of an integrated circuit chip, and/or as a building block for a large system. The apparatus (10) is connected to a communications bus (40) which receives apparatus parameter, topological, and microinstruction information from a host processor and/or memory (EPROM). The apparatus includes numerous functional blocks (20), a core (30), and a parametric/microinstruction bus (35). The functional blocks include serial (62,66) and parallel ports (68), D/A (54) and A/D (52) converters, and programmable signal processors (300) which serve to process signal data and are connected in any desired manner through a switching matrix (160) located in the core. The topology of the switching matrix (160) is received via the communications bus (40).

Abstract: A static random access memory (SRAM) having a reduced access time for reading and reduced probability of inadvertent writing operations. Switching circuits (multiplexers) that are used to connect column bit lines with reading and writing circuits of the memory are divided into separate circuits for use during read and write operations. A recovery pulse is applied only to bit lines of a column just written to by use of the driving circuits through the same column line switching circuits.