Abstract: A programmable interconnect system having a plurality of PICs connected via a plurality of buses where each bus may have two or more branches connecting the PICs is disclosed. Generally speaking, for a system with N PICs, there can be N−1 different type of buses having 2 to N corresponding branches to the N PICs. For example, for a four PIC programmable interconnect system, there can be three types of buses connecting the PICs, a two-branch bus, a three-branch bus, and a four-branch bus. Note that the term “bus” refers to one or more signal paths connecting the PICs. For each type of buses, there can be several layouts.

Abstract: A hardware-based emulator is partitioned onto two boards. An emulation board has field-programmable gate array (FPGA) chips mounted on a top surface, and connection posts protruding through to the bottom surface. The I/O pins of the FPGA chips that carry emulated signals are connected to the connection posts but not directly to other FPGA chips on the emulation board. An interconnection board has a grid of wire-wrap posts. The tops of the wire wrap-posts mate with the connection posts when the emulation board is plugged in to the interconnection board. The wire-wrap posts extend through the interconnection board and out the bottom surface. Interconnection is made by wire-wrap wires wound around the wire-wrap posts. Thus interconnection between FPGA chips on the emulation board is made by wire-wrap on the interconnection board, while the logic gates are emulated in the FPGA chips on the separate emulation board.