Abstract: Time measurement apparatus comprising a delay line having a plurality of taps, each tap having an associated latch. An inverting AND gate has its output connected to an initial tap of the delay line, an input signal having two conditions connected to one of its inputs, and has its other input connected to a later tap of the delay line.The arrangement causes oscillation of the delay line in the presence of the first condition of the input signal. A counter counts the oscillations of the delay line, and the latches are caused to operate simultaneously on the second condition of the input signal.The value stored in the counter and the pattern stored in the latches is used to derive the duration of the first condition.