Patents Assigned to Logic Research Co., Ltd.
  • Patent number: 7498897
    Abstract: An impedance matching circuit, a semiconductor element and a radio communication device using the same, adjusting bandwidth while permitting it to be constructed on the semiconductor element by reducing its occupation area. Since a reactance compensating distributed constant line (31) compensates reactance (BL, XS) of a load (6) and a quarter-wave transmission line (32) and an impedance inverting distributed constant line (33) composing an impedance inverting circuit (K inverter or J inverter) corresponding to the degree of impedance (ZL, ZS) of the load (6) match the impedance (ZL, ZS) of the compensated load (6) and output the input signals (SI1, SI2) at the preset bandwidth, adjustment of bandwidth can be made while miniaturizing the impedance matching circuit (7a) by shortening the line length of the reactance compensating distributed constant line (31) and the quarter-wave transmission line (32).
    Type: Grant
    Filed: March 4, 2004
    Date of Patent: March 3, 2009
    Assignees: Japan Science and Technlogy Agency, Logic Research Co., Ltd.
    Inventors: Keiji Yoshida, Haruichi Kanaya, Tadaaki Tsuchiya
  • Patent number: 6625783
    Abstract: A flexible and reliable state machine and a semiconductor device using the state machine are provided. A state machine includes a memory circuit (1), a comparator circuit (2), an analyzer circuit (3) and an arithmetic circuit (4). The memory circuit (1) receives and holds data (5-1a) indicative of the next state, and outputs it as data (5-1b) indicative of present state. The comparator circuit (2) compares the date (5-2a) indicative of the present or next state and generates a state flag (6-2b). The analyzer circuit (3) decodes a state flag (6-3a) and generates the control signal (7-3b) for controlling operation of the arithmetic circuit (4). Based on a control signal (7-4a), the arithmetic circuit (4) operates on the data (5-4a) indicative of the present state and generates data (5-4b) indicative of the next state.
    Type: Grant
    Filed: October 10, 2001
    Date of Patent: September 23, 2003
    Assignee: Logic Research Co., Ltd.
    Inventor: Kei Yamanaka