Patents Assigned to Logic Systems, Inc.
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Patent number: 11854700Abstract: A method of and system for the determination of MMI to assist in injury and exposure claim adjudication by assisting stakeholders access to a metric system analysis based on an objective claim data set. The method and system utilizes a recovery score index for determining whether the individual is medically stable and one or more recovery phase classifications for determining that available treatment has been provided to the individual. Based on these metrics, the present invention is able to determine a highly accurate and objective maximum medical improvement status and dating assignment.Type: GrantFiled: December 6, 2017Date of Patent: December 26, 2023Assignee: Alchemy Logic Systems, Inc.Inventors: John William Alchemy, Jerry Lee Artz, Daniel Ryan Penn
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Patent number: 11853973Abstract: A method and system enhances the execution of the telemedicine impairment repair process (IRP) to claim closure by assisting all stakeholders by monitoring the process and reminding the stakeholders of the stakeholder roles and responsibilities to maintain a prudent time frame for the reported injury and/or illness. The method of and system for executing an impairment repair process addresses flaws in the current process by implementing timing guided by legislation and best medical practice. Key aspects of the impairment repair process are addressed to ensure prudent timing by assuring accuracy of claim development, monitoring, and initiating communication to closure. The process is implemented in multiple stages including, assessment, documentation, prescribed treatment, and analysis of outcome.Type: GrantFiled: January 25, 2017Date of Patent: December 26, 2023Assignee: Alchemy Logic Systems, Inc.Inventors: John William Alchemy, Bruce Brandon Wilson
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Patent number: 11848109Abstract: A system and method is implemented to provide a construction of three separate timelines for comparison and analysis including a query to a historical accurate database. One or more data sets are compared to a high accuracy database that contains reviewed and accurate historical impairment data. An analysis of the historical data can facilitate the output of a temporary impairment rating, apportionment, future care demand of resources and one or more recommendations for the most effective manner to achieve MMI. The collection of outputs are used to create an injury map nexus.Type: GrantFiled: July 27, 2020Date of Patent: December 19, 2023Assignee: Alchemy Logic Systems, Inc.Inventors: John William Alchemy, Jerry Lee Artz, Roger Bastow
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Patent number: 11625687Abstract: A method and system for quantifying a lack of parity for a subjective data set and an objective data set within an injury profile report. The method and system analyzes and inspects each subjective and objective data set and compares these data sets to a historical accuracy database to find a lack of agreement or non-parity of the data sets. The method and system quantifies the lack of parity, creates an injury profile report and proscribes any functional limitations for the injured worker. The output can be used to assign safer and more accurate functional limitations and assign safer and more accurate functional limitations to support a safer return to work event for the inured worker after injury.Type: GrantFiled: October 15, 2019Date of Patent: April 11, 2023Assignee: Alchemy Logic Systems Inc.Inventors: John William Alchemy, Jerry Lee Artz, Bruce Brandon Wilson
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Publication number: 20220391993Abstract: A method and system teaches unique applications of logic and statistics to medical processes to obtain substantially improved accuracy in the measurement of a examinee's pathology due to an injury. The method and the system incorporate strict protocols, or “Administrative Rule Sets” to direct the examination for the purpose of obtaining an optimal data set, from which a rating of the impairment due to the pathology resulting from an injury may be determined. Additionally, within this method and system, a statistical analysis may additionally assist in obtaining an improved accuracy of impairment ratings. Consequently, the errors in the impairment rating presently carried forward through the disability, care and compensation phases of the process are now avoided.Type: ApplicationFiled: August 19, 2022Publication date: December 8, 2022Applicant: Alchemy Logic Systems Inc.Inventors: John William Alchemy, Daniel Robert Brown, Daniel Ryan Penn, Joshua Ryan Moore, Jerry Lee Artz, Anne Elise Weilepp, Marten Lee Thompson
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Patent number: 11461848Abstract: A method and system teaches unique applications of logic and statistics to medical processes to obtain substantially improved accuracy in the measurement of a examinee's pathology due to an injury. The method and the system incorporate strict protocols, or “Administrative Rule Sets” to direct the examination for the purpose of obtaining an optimal data set, from which a rating of the impairment due to the pathology resulting from an injury may be determined. Additionally, within this method and system, a statistical analysis may additionally assist in obtaining an improved accuracy of impairment ratings. Consequently, the errors in the impairment rating presently carried forward through the disability, care and compensation phases of the process are now avoided.Type: GrantFiled: January 14, 2016Date of Patent: October 4, 2022Assignee: Alchemy Logic Systems, Inc.Inventors: John William Alchemy, Daniel Robert Brown, Daniel Ryan Penn, Joshua Ryan Moore, Jerry Lee Artz, Anne Elise Weilepp, Marten Lee Thompson
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Patent number: 9402026Abstract: One aspect of the present invention provides a simple, cost-effective, efficient solution directed to the generation of the source material for the generation of still panoramic images. The precision optical alignment among all the mounted lenses, provided by the precision rectangular mounting rig, greatly reduces or eliminates stitching errors. Stitching errors often result in noticeable defects in the final image which will require human technical assistance to remedy (if the defect is of the repairable type). Accurate, error-free, source material enables virtually full automation of the panoramic imaging process; wherein the end product is high quality and quickly achieved.Type: GrantFiled: January 4, 2014Date of Patent: July 26, 2016Assignee: Circular Logic Systems, Inc.Inventor: Patrick A. St. Clair
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Patent number: 8780235Abstract: This invention provides an image processing method which for noise reduction and sensitization for an ordinary video camera. The noise reduction processing locates a bright pixel and averages brightness by adding the pixel accumulated by ratio in accordance with the geometric series, and to a dark pixel, carrying out the processing of noise reduction which averages brightness by adding the pixel accumulated by ratio in accordance with the geometric series and the processing of sensitization in the condition that a magnification of intensification is greater than 1, determine that the pixel moves or not, if the pixel is moving, it is used to carry out processing of sensitization only, and if the pixel is still, choose it is used to carry out the processing of sensitization and noise reduction.Type: GrantFiled: June 13, 2012Date of Patent: July 15, 2014Assignee: Logic & Systems, Inc.Inventor: Masahiro Kobayashi
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Publication number: 20130176464Abstract: This invention provides an image processing method which for noise reduction and sensitization for an ordinary video camera. The noise reduction processing locates a bright pixel and averages brightness by adding the pixel accumulated by ratio in accordance with the geometric series, and to a dark pixel, carrying out the processing of noise reduction which averages brightness by adding the pixel accumulated by ratio in accordance with the geometric series and the processing of sensitization in the condition that a magnification of intensification is greater than 1, determine that the pixel moves or not, if the pixel is moving, it is used to carry out processing of sensitization only, and if the pixel is still, choose it is used to carry out the processing of sensitization and noise reduction.Type: ApplicationFiled: June 13, 2012Publication date: July 11, 2013Applicant: LOGIC & SYSTEMS, INC.Inventor: Masahiro KOBAYASHI
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Patent number: 7030777Abstract: A system and method for generating remote incursion alerts in response to incursion detected by incursion transmitter units, such as at traffic cones, posts, barricades and signage. Alerts are generated in response to impacts detected at the safety icons within an incursion transmitter (or transceiver) and transmitted to one or more incursion receiver units which annunciate the alert with audio, lights, and or tactile output to warn construction crews of possibly impending danger. The alert signals may be communicated over a wired connection or a wireless communication link. Alert signals wirelessly communicated are preferably repeated by other incursion transmitters which are each coupled to a receiver to form a transceiver, wherein the distance and conditions over which the wireless alert signals may be communicated is extended. The incursion receiver may generate area alerts, or personal alerts, such as comprising the generation of audio, physical outputs, or light signals.Type: GrantFiled: November 5, 2002Date of Patent: April 18, 2006Assignee: Logic Systems, Inc.Inventors: Craig Nelson, Robert E. Bos
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Patent number: 6346826Abstract: A programmable gate array device (10) has a repeating block of circuitry (16) that includes a lowest metal layer. The repeating block of circuitry (16) includes a row of combinatorial blocks (20) and a row of flip flop circuitry (22). A number of metal segments (38) run perpendicular to the row of combinatorial blocks (20). The metal segments (38) are formed in a middle metal layer. A customizable metal layer forms a top metal layer (40).Type: GrantFiled: December 23, 1998Date of Patent: February 12, 2002Assignee: Integrated Logic Systems, IncInventors: Hugh Norman Chapman, Michael Robert Whaley
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Patent number: 6246967Abstract: The present invention is a Weight Verification Device (WVD) that stamps a weight transaction record with a digital signature so that transaction data may be verified at a later time. The WVD is an Application Specific Integrated Circuit (ASIC) device that is installed in a sealed digital weight indicator. When a vehicle is weighed using this digital weight indicator, a weight transaction record is stamped with a digital signature and stored in a computer. The WVD may be used to confirm that the inbound and outbound weights and the date and time are accurate, that the transaction data have not been tampered with, and that the transaction as a whole has not been modified in any way since the time the transaction record was created. The digital signature stored with the transaction data is based on a secure hash of the transaction data and a “private” key belonging to an inspector from the Weights and Measures Department or a designated representative.Type: GrantFiled: April 22, 1998Date of Patent: June 12, 2001Assignee: Interface Logic Systems, Inc.Inventors: Charles M. Libicki, Harold W. Cheney, III
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Patent number: 6237098Abstract: The present invention is a Weight Verification Device (WVD) that stamps a weight transaction record with a digital signature so that transaction data may be verified at a later time. The WVD is an Application Specific Integrated Circuit (ASIC) device that is installed in a sealed digital weight indicator. When a vehicle is weighed using this digital weight indicator, a weight transaction record is stamped with a digital signature and stored in a computer. The WVD may be used to confirm that the inbound and outbound weights and the date and time are accurate, that the transaction data have not been tampered with, and that the transaction as a whole has not been modified in any way since the time the transaction record was created. The digital signature stored with the transaction data is based on a secure hash of the transaction data and a “private” key belonging to an inspector from the Weights and Measures Department or a designated representative.Type: GrantFiled: February 24, 1999Date of Patent: May 22, 2001Assignee: Interface Logic Systems, Inc.Inventor: Charles M. Libicki
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Patent number: 5550649Abstract: A telephone terminal adapted for business or home use that includes the ability to receive and send facsimiles, a voice answering function and a computer modem. Various input and output devices may be used for the facsimile function. A voice annotated facsimile may be sent and received. At the same time the facsimile is viewed on a video monitor or ordinary television set, an accompanying voice message is heard through the sound system of the monitor or television set. The terminal has an architecture including a central processor and an internal bus structure to which several types of memory, various input-output devices and an interface with the telephone line are connected, among others.Type: GrantFiled: May 14, 1992Date of Patent: August 27, 1996Assignee: Current Logic Systems, Inc.Inventors: John J. Wong, Paul S. Lui
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Patent number: 5537631Abstract: A memory management technique is provided for managing the storage and retrieval of data within an ARAM memory array such that both fault tolerant data and fault non-tolerant data can be stored within the ARAM array without such data becoming corrupted due to the faulty bits within the ARAM memory. The memory management technique of the present invention also includes a method for creating a novel facsimile header format which makes it less likely for the header information to be corrupted due to faulty memory cells within the ARAM memory array.Type: GrantFiled: March 21, 1994Date of Patent: July 16, 1996Assignee: Current Logic Systems, Inc.Inventors: John J. Wong, Rick Culver
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Patent number: 5455525Abstract: A structured logic array is divided into hierarchical levels. At a highest level (the chip level), blocks are interconnected by a system of chip busses. A block interface couples each block to the chip bus system to allow the blocks to communicate with each other. At a lower level, each block includes sectors, each sector being coupled to a block bus system by a sector interface. The block bus system interconnects the sectors in each block to allow the sectors to communicate with each other. The block bus system is also coupled to the block interface to allow signals to be transferred between the block bus system and the chip bus system. At a lowest level, each sector includes a plurality of logic elements. The logic elements are interconnected by a sector bus system. The sector bus system is coupled to the sector interface to allow for the transfer of signals between the sector bus system and the block bus system.Type: GrantFiled: December 6, 1993Date of Patent: October 3, 1995Assignee: Intelligent Logic Systems, Inc.Inventors: Walford W. Ho, Chao-Chiang Chen, Yuk Y. Yang
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Patent number: 4727493Abstract: A new ensemble of logic elements organized in an array and a method of forming the same wherein the architecture includes a main field of transistor elements formed on a substrate material. A group of load transistors and an array of logic gates are formed on the substrate and are located within the main field of transistors. At least one routing channel is provided in the main field, and an input/output structure is located on the substrate. A region of flip-flop elements, also located within the main field, may be provided. Preferably, a plurality of such groups, arrays and regions are formed in parallel strips extending across the main field, and a perpendicular bussing channel also extends across the field to divide the main field into component arrays. The logic gates may be configurable structures or dedicated inverters, and a plurality of input/output structures may be employed. The method includes the electrical interconnection of these elements into logic terms to form an integrated circuit.Type: GrantFiled: May 4, 1984Date of Patent: February 23, 1988Assignee: Integrated Logic Systems, Inc.Inventor: David L. Taylor, Sr.
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Patent number: 4684967Abstract: A transistor cell element that may be used alone or in a matrix array in large scale integrated circuits includes a substrate onto which an isolation region is fabricated. Inner and outer charge carrier regions having a high density of first charge carriers is formed in the substrate to define a channel region therebetween. The inner carrier region is adjacent the isolation region so that the channel region extends in a closed loop from said isolation region, around the inner carrier region and back to the isolation region, with the outer carrier region surrounding the isolation and channel regions. The channel region has a low density of second charge carriers, having opposite charge than the first charge carriers, and a gate structure including a conductive band and an insulating layer is formed over the channel region. In one alternate embodiment, additional isolation regions may be provided with these regions interrupting the channel region.Type: GrantFiled: May 4, 1984Date of Patent: August 4, 1987Assignee: Integrated Logic Systems, Inc.Inventors: David L. Taylor, Sr., Hugh N. Chapman
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Patent number: 4590581Abstract: A simulation model is provided which comprises a combination of the physical device to be modeled and means for controlling the physical device at normal operating speeds so as to avoid loss of data or of accumulated functions. Specifically, the physical device to be modeled is connected through a micro-system simulation means which can accept any of a wide variety of external devices and which includes the logic circuitry and control means necessary to allow the physical device to be stimulated and the resulting behavior observed under external control. Data and logic state patterns are preserved by effective control of the starting, stopping, cycling and resetting of the physical device.Type: GrantFiled: May 9, 1983Date of Patent: May 20, 1986Assignee: Valid Logic Systems, Inc.Inventor: L. Curtis Widdoes, Jr.