Abstract: A deserializer is provided. The deserializer includes a data receiver, an RCC transmitter, an I2C master, a command determination device, a video transmitter, a video processing device and an I2S transmitter. The data receiver analyzes raw data sent to the deserializer to obtain audio data, video data and/or command data. The I2S transmitter sends the audio data to the outside of the deserializer. The video processing equipment performs a format conversion on the video data and sends the video data to the outside of the deserializer. The command determination device determines the command data, and sends the command data to the outside of the deserializer in response to a determination result indicating that the command data is a deserializer external command.

Abstract: A circuit and a method for removing spread spectrum are provided. The circuit includes a data clock recovery module and a clock extraction module that are connected. The data clock recovery module performs clock recovery on an input signal carrying spread spectrum information to obtain a parallel clock signal and a first signal, where the parallel clock signal includes frequency information and phase information, and the first signal includes the frequency information. The clock extraction module divides a frequency of the parallel clock signal to obtain a reference clock signal; acquires a feedback clock signal based on the first signal; acquires a de-spread clock signal based on the reference clock signal and the feedback clock signal, where the de-spread clock signal includes the phase information and does not include the frequency information; and divides a frequency of the de-spread clock signal to obtain an output clock signal.

Abstract: A circuit and a method for removing spread spectrum are provided. The circuit includes a data clock recovery module and a clock extraction module that are connected. The data clock recovery module performs clock recovery on an input signal carrying spread spectrum information to obtain a parallel clock signal and a first signal, where the parallel clock signal includes frequency information and phase information, and the first signal includes the frequency information. The clock extraction module divides a frequency of the parallel clock signal to obtain a reference clock signal; acquires a feedback clock signal based on the first signal; acquires a de-spread clock signal based on the reference clock signal and the feedback clock signal, where the de-spread clock signal includes the phase information and does not include the frequency information; and divides a frequency of the de-spread clock signal to obtain an output clock signal.

Abstract: A data processing method is applied to a digital interface, which includes: reading data cached by a data source, where the data source includes a video source and an auxiliary data source; outputting video data, if the video data cached by the video source is not empty, where when the video data is output, corresponding position marks are at start and end positions of a frame structure of the video data and at start and end positions of a row structure of the video data; and outputting auxiliary data, if the video data cached by the video source is empty, the auxiliary data cached by the auxiliary data source is not empty and the frame structure or the row structure of the video data has been output, where when the auxiliary data is output, corresponding position marks are at a start position and an end position of the auxiliary data.

Abstract: A data processing method is applied to a digital interface, which includes: reading data cached by a data source, where the data source includes a video source and an auxiliary data source; outputting video data, if the video data cached by the video source is not empty, where when the video data is output, corresponding position marks are at start and end positions of a frame structure of the video data and at start and end positions of a row structure of the video data; and outputting auxiliary data, if the video data cached by the video source is empty, the auxiliary data cached by the auxiliary data source is not empty and the frame structure or the row structure of the video data has been output, where when the auxiliary data is output, corresponding position marks are at a start position and an end position of the auxiliary data.

Abstract: A serializer includes: an I2C controller, an I2C command analysis circuit, a system control circuit, a low-speed data transmission circuit, a high-speed data conversion circuit, a low-speed data processing circuit, a parallel-serial conversion bidirectional circuit, a serial-parallel conversion circuit, a protocol analysis circuit, a video data processing circuit and an I2C receiver. The serializer can receive the external control command from the external controller through the I2C controller, and can also receive the external control command and the internal control command through the parallel-serial conversion bidirectional circuit. In addition, the serializer can also receive the video data from the external video source through the serial-parallel conversion circuit, and receive the audio data from the external source through the I2C receiver. Therefore, the serializer in the present disclosure can be applied to both two application scenarios, which is more flexible in application.

Abstract: A method and a system for automatically adjusting intensity of a signal outputted by an HDMI transmitter are provided. With the method, a length of an HDMI transmission line between the HDMI transmitter and an HDMI receiver is determined. A swing amplitude and a pre-emphasis intensity of the signal outputted by the HDMI transmitter are determined based on the length of the HDMI transmission line and a frequency of the signal outputted by the HDMI transmitter. An HDMI output drive circuit is configured based on the swing amplitude and the pre-emphasis intensity.

Abstract: A serializer includes: an I2C controller, an I2C command analysis circuit, a system control circuit, a low-speed data transmission circuit, a high-speed data conversion circuit, a low-speed data processing circuit, a parallel-serial conversion bidirectional circuit, a serial-parallel conversion circuit, a protocol analysis circuit, a video data processing circuit and an I2C receiver. The serializer can receive the external control command from the external controller through the I2C controller, and can also receive the external control command and the internal control command through the parallel-serial conversion bidirectional circuit. In addition, the serializer can also receive the video data from the external video source through the serial-parallel conversion circuit, and receive the audio data from the external source through the I2C receiver. Therefore, the serializer in the present disclosure can be applied to both two application scenarios, which is more flexible in application.

Abstract: A method and a system for automatically adjusting intensity of a signal outputted by an HDMI transmitter are provided. With the method, a length of an HDMI transmission line between the HDMI transmitter and an HDMI receiver is determined. A swing amplitude and a pre-emphasis intensity of the signal outputted by the HDMI transmitter are determined based on the length of the HDMI transmission line and a frequency of the signal outputted by the HDMI transmitter. An HDMI output drive circuit is configured based on the swing amplitude and the pre-emphasis intensity.

Abstract: A conversion apparatus, a storage device and a method for manufacturing the same are provided. The storage device may include a DDR storage layer, a DDR interface layer, a conversion logic circuit layer, and a peripheral interface layer. The peripheral interface layer may include a GDDR interface layer or a PCIe interface layer. The conversion logic circuit layer may process, by using DDR storage logic, data obtained through the peripheral interface layer and transfer processed data to the DDR interface layer, or process, by using GDDR storage logic, data obtained through the DDR interface layer and transfer processed data to the peripheral interface Layer. The DDR storage layer may be connected to the DDR interface layer, so that the conversion logic circuit layer can convert the storage logic of the data from DDR to GDDR or from GDDR to DDR.

Abstract: A conversion apparatus, a storage device and a method for manufacturing the same are provided. The storage device may include a DDR storage layer, a DDR interface layer, a conversion logic circuit layer, and a peripheral interface layer. The peripheral interface layer may include a GDDR interface layer or a PCIe interface layer. The conversion logic circuit layer may process, by using DDR storage logic, data obtained through the peripheral interface layer and transfer processed data to the DDR interface layer, or process, by using GDDR storage logic, data obtained through the DDR interface layer and transfer processed data to the peripheral interface Layer. The DDR storage layer may be connected to the DDR interface layer, so that the conversion logic circuit layer can convert the storage logic of the data from DDR to GDDR or from GDDR to DDR.

Abstract: A high speed signal drive circuit includes a D-PHY drive signal generation module, a C-PHY drive signal generation module, a drive signal selection module and a multiplex drive module. An output terminal of the D-PHY drive signal generation module and an output terminal of the C-PHY drive signal generation module are both connected to an input terminal of the drive signal selection module. An output terminal of the drive signal selection module is connected to an input terminal of the multiplex drive module. The drive signal selection module controls control switches of the multiplex drive module to be on and off based on a D-PHY drive signal or a C-PHY drive signal, so that the multiplex drive module functions as a D-PHY drive circuit or a C-PHY drive circuit. Thus, dual functions of the D-PHY drive circuit and the C-PHY drive circuit can be realized.

Abstract: A cascade complementary source follower and a controlling circuit are provided. The source follower circuit includes: a source follower circuit including at least two MOS transistors, and a feedback circuit configured to clamp a voltage on a MOS transistor that provides an output voltage in the source follower circuit and to change a gate-source voltage of the MOS transistor by adjusting a bias current supplied to the MOS transistor, so that an output voltage can precisely follow an input voltage.

Abstract: A circuit for generating differential reference voltages, a circuit for detecting a signal peak, and an electronic device. In the circuit for generating reference voltages, a common-mode extraction circuit receives a first differential signal and a second differential signal, extracts a common-mode level from the first differential signal and the second differential signal, and applies the common-mode level to a non-inverting input terminal of a first operational amplifier. The first operational amplifier, a main control switch, a first voltage dividing resistor, a second voltage dividing resistor, and a first direct current power source constitute a feedback loop, to generate differential reference voltages matching with the common-mode level. Adjusting a current provided by the first direct current power source can change the differential reference voltages, obtaining a reference for to-be-detected amplitude of the signals.

Abstract: A switch circuit and a high-speed multiplexer-demultiplexer are provided. The switch circuit includes an equalization module and an MOS transistor. A gate of the first MOS transistor is connected to an output terminal of the equalization module. An input terminal of the first MOS transistor is connected to a signal source. An output terminal of the first MOS transistor is connected to a subsequent circuit. The equalization module is configured to: supply a turning-on signal to the first MOS transistor in a case that an operation signal is acquired, to turn on the first MOS transistor; and generate a compensation signal for compensating an attenuation of the signal transmitted through the first MOS transistor, and apply the compensation signal to the gate of the first MOS transistor. The switch circuit operates in response to the operation signal.

Abstract: A signal extension system is provided according to the present disclosure, which includes: a transmitting side chip and a receiving side chip connected to the transmitting side chip. The transmitting side chip is configured to receive high-definition video data and transmit the high-definition video data to the receiving side chip after performing first color space conversion, low compression, parallel-serial coding on the high-definition video data sequentially. The receiving side chip is configured to receive the high-definition video data transmitted from the transmitting side chip and output the high-definition video data to a display device for display after performing serial-parallel decoding, low decompression, and second color space conversion on the received high-definition video data. With the above signal extension system, a transmission distance of the high-definition video data is extended.

Abstract: A Biphase Mark Coding (BMC) transceiver is provided. In the BMC transceiver, an operational amplifier operating in a time division multiplexing manner is used. The operational amplifier is configured as a unity gain buffer, and it is determined whether the BMC transceiver operates as a transmitter or a receiver by selecting different input switches and output switches. In a transmitting mode, a bias current of an input differential pair transistor of the operational amplifier is changed, to change a slew rate, so as to obtain an output waveform with adjustable rising/falling edges of the transmitter.

Abstract: A bidirectional signal conditioning chip for a USB Type-C cable and a USB Type-C cable are provided. The chip includes a memory, a processor and a transfer driver. The transfer driver is configured to regenerate and transmit a high speed signal; the memory is configured to store a program code; the processor is configured to call the program code, and perform the following operations when the program code is executed: determining a data transmission direction and a type supported by transmitted data of the USB Type-C cable; configuring on-off states of buffers in the transfer driver based on the data transmission direction and the supported type, so that a data output direction of the transfer driver is consistent with the data transmission direction.

Abstract: A biphase mark coding transmitter is provided. In the biphase mark coding transmitter, a delay control unit performs equal-interval delay processing on data transmitted by a data coding and protocol processing unit. Then, the current-steering digital-to-analog converter is controlled to charge or discharge a resistance-capacitance circuit to obtain an accurately-controlled conversion time. Data with the controlled conversion time is driven to a CC by a unity-gain buffer to generate an output waveform. The technical solution solves the technical problem of a mutual influence between power source systems of a traditional BMC transmitter which is a digital module and a traditional BMC receiver which is an analog module, and the technical problem of a large noise of a power switch and large consumption of chip area and power which are resulted from digital buffers driven by equal-interval data or clocks in a traditional BMC transmitter.

Abstract: A matrix switcher is provided. A code rate of an ultra-high-definition video signal is reduced on the premise that the quality of the ultra-high-definition video signal is not affected through performing a Color Space Conversion (CSC) process and/or a Digital Stream Compression (DSC) process on the ultra-high-definition video signal at the transmitting side chip, thereby reducing a bandwidth required in conversion, switch and transmission of the ultra-high-definition video signal. A matrix switch chip with a low cost and general performance is used. Then, a corresponding DSC data decompression process and/or CSC process are performed at the receiving side to recover the performance of the ultra-high-definition video signal.