Abstract: Disclosed are a system and method for generating a symmetrically balanced output to accomplish a plurality of predefined properties. The method comprises a step of receiving a plurality of registers with B bits, an expression length, and a plurality of operators through a receiving module. The method then includes a step of generating a random expression population through a random expression population generation module. Further, the method includes the step of computing a fitness value of the random expression population through a fitness function module. The method then includes the step of providing registers with B bits if a plurality of output bits are having an equal number of 1s and 0s through a conditional module. The conditional module performs mutation in the operators if the output bits are not having an equal number of 1s and 0s.

Abstract: Disclosed are a system and method for generating a symmetrically balanced output to accomplish a plurality of predefined properties. The method comprises a step of receiving a plurality of registers with B bits, an expression length, and a plurality of operators through a receiving module. The method then includes a step of generating a random expression population through a random expression population generation module. Further, the method includes the step of computing a fitness value of the random expression population through a fitness function module. The method then includes the step of providing registers with B bits if a plurality of output bits are having an equal number of 1s and 0s through a conditional module. The conditional module performs mutation in the operators if the output bits are not having an equal number of 1s and 0s.