Abstract: Provided are methods and apparatuses for use in wireless communication between a transmitter having plural transmit antennas and a receiver having plural receive antennas. A first data stream using a first transmit antenna weight vector and a second data stream using a second transmit antenna weight vector simultaneously are transmitted to the receiver. In addition, a first perturbation signal corresponding to the first transmit antenna weight vector and a second perturbation signal corresponding to the second transmit antenna weight vector are transmitted. Feedback regarding the first transmit antenna weight vector and the second transmit antenna weight vector is received from the receiver and is utilized to modify the first transmit antenna weight vector and the second transmit antenna weight vector.

Abstract: A computer-based test method and apparatus for measuring DC current drawn by an integrated circuit. The apparatus has a plurality of current measurement ranges and is first initialized to a selected one of the measurement ranges. Next, the apparatus measures the DC current drawn by the integrated circuit in the selected measurement range and increments the selected measurement range if the measured DC current is out of the selected measurement range. The apparatus repeats the steps of measuring and incrementing until the measured DC current is in the selected measurement range. The measured DC current is then compared to a specification limit for the integrated circuit.

Abstract: A capacitor that is a metal to polysilicon capacitor. The capacitor is fabricated by forming a field oxide layer on a substrate. Then, a polysilicon segment is formed on the field oxide layer. This polysilicon segment forms a polysilicon bottom plate for the capacitor. A dielectric layer is formed and planarized. An opening is made in the dielectric layer to expose a portion of the polysilicon segment. Then, an oxide layer is formed on exposed portions of the polysilicon segment. A metal segment is formed on the oxide layer over the opening, wherein the metal segment forms a top-plate for the semiconductor device.

Abstract: A voltage comparator circuit includes a comparator 42 having a first comparison input, a second comparison input and first and second switched current memories 52, 58 (e.g., switched FETs) connectable, respectively, to the first and second comparator inputs for input voltage offset compensation. In use, during a storage phase, a current value is stored in the switched current memory for each of the first and second comparison inputs and, during a comparison phase, the stored current values are used to compensate for voltage offsets between the comparison inputs.

Abstract: A semiconductor die is disposed on a side of an optically-transmissive preformed planar structure (interposer), and an optical element is disposed on an opposite side of the interposer. The interposer may be provided with through holes extending at least partially into the die side, and electrical probes in the through holes, for making contact to raised conductive bumps on the die. The interposer may be provided with raised portions for locating the optical element at a predetermined distance away from the die. The interposer may be provided with darkened areas for preventing light from impacting selected areas of the die.

Abstract: An integrated circuit device package of this invention includes a flexible substrate having an upper patterned insulative layer, and a lower patterned conductive layer including a plurality of package leads. An integrated circuit die is fixed within a void of the upper surface of the flexible substrate. Electrical connections between the integrated circuit die and the package leads are provided. A rigid upper protective layer is present. The rigid upper protective layer encloses the integrated circuit die, and at least partially covers the top surface of the upper insulative layer. The semiconductor device package further comprises a rigid or semi-rigid metal lower protective layer opposite the upper protective layer including a ground plane proximal to the electrical leads and a power plane distal to the leads. Methods of production are also given.

Abstract: An electronic camera includes a photosensor array that is supported by a housing. The photosensor array includes a plurality of binary diffractive lens elements for forming a substantially identical light image on laterally spaced areas of a surface respectively. A plurality of photosensors are disposed on the surface within the laterally spaced areas for receiving different portions of the light image respectively such that the photosensors in aggregation receive substantially all of the light image. The photosensors can have constant spacings therebetween, and the lenses have spacings therebetween that increase away from a predetermined point in the array. Alternatively, the lenses can have constant spacings therebetween, and the photosensors have spacings therebetween that increase away from a predetermined point in the array.

Abstract: An integrated circuit fabrication method and apparatus to improve the design cycle time for implementing an electrical system in silicon. The invention uses predefined core, or cell, patterns to provide some of the functionality for a system design. The cores are interconnected using thick wire conductors and solder bumps so that conductive paths that do not lie within the plane of the substrate of the silicon chip containing the cores are provided. Since the conductive paths do not lie on the process surface of the chip, the topographical design of the chip is not affected by the interconnections. Further, the thick wire conductors result in essentially zero propagation delay so that timing design errors are greatly reduced, or eliminated, in the design cycle. The invention allows for a rapid prototype of the entire design to be produced early in the design cycle. In one embodiment, customer logic is arranged around the periphery of the substrate while the core cells are in the middle of the substrate.

Abstract: A radiation hardened NMOS transistor structure suited for application to radiation hardened CMOS devices, and the method for manufacturing it is disclosed. The new transistor structure is characterized by "P" doped guard bands running along and immediately underlying the two bird's beak regions perpendicular to the gate. The transistor and the CMOS structure incorporating it exhibit speed and size comparable to those of conventional non-rad-hard CMOS structure, relatively simple manufacturing, and excellent total-dose radiation hardness.