Abstract: A method and apparatus which uses a plating electrode in an electrolyte bath. The plating electrode works to purify an electrolyte polishing solution during the electro-polishing process. Preferably, the plating electrode is employed in a closed loop feedback system. The plating electrode may be powered by a power supply which is controlled by a controller. A sensor may be connected to the controller and the sensor may be configured to sense a characteristic (for example, but not limited to: resistance, conductance or optical transmission, absorption of light, etc.) of the electrolyte bath, which tends to indicate the level of saturation. Preferably, the plating electrode is easily replaceable.

Abstract: The present invention is an apparatus and system for providing a high quality spiral inductor in an integrated circuit environment. A layer of inductor may be placed within the metal layers along with negative capacitance generation circuitry of the present invention to compensate for the capacitance associated with the metal layers adjacent to the inductor to provide a higher quality factor for the inductor. Advantageously, circuitry of the present invention may be employed within an integrated circuit without modifying the layer structure of the integrated circuit. Additionally, values of the components of the circuitry may be selectively and independently chosen to synthesize a variable range of negative capacitance.

Abstract: In exemplary embodiments, a method and computer program product for predicting quiescent current variation of an integrated circuit die include steps of: (a) receiving as input a value of a derating factor from a process monitor cell on an integrated circuit die and an on-chip variation of the derating factor; (b) constructing a curve fitting formula for estimating a quiescent current of the integrated circuit die as a function of the derating factor; (c) calculating minimum and maximum values of the quiescent current from the curve fitting formula, the value of the derating factor from the process monitor cell, and the on-chip variation of the derating factor to generate an estimate of minimum and maximum values for the quiescent current; and (d) generating as output the estimated minimum and maximum values of the quiescent current.

Abstract: A tool for designing integrated circuits that optimizes the placement and timing of memory blocks within the circuit. Given a manufactured slice that has a number of blocks already diffused and logically integrated, the memory generation tool herein automatically considers the available diffused memory and the gate array of the slices to configure and optimize them into a customer's requirements for memory. The memory generation tool has a memory manager, a memory resource database, a memory resource selector, and a memory composer. Together these all interact to generate memories from the available memories within the memory resource database. The memory composer actually generates the RTL logic shells for the memories, and outputs the memory designs in Verilog, VHDL, or other tool synthesis language. Once a memory is created, it is tested.

Abstract: A bus that may be used in an integrated circuit chip. The bus generally comprises a master interface, a slave interface, and a control logic. The master interface may be configured to (i) receive an early command signal having a predetermined timing relationship to a first clock edge and (ii) present a bus wait signal proximate a second clock edge. The slave interface may be configured to (i) present a command signal a delay after the first clock edge and (ii) receive a slave wait signal. The control logic may be configured to (i) register the early command signal to generate the command signal and (ii) convert the slave wait signal into the bus wait signal.

Abstract: A system and method for providing a method for reducing artifacts in a video sequence of image frames is disclosed. The method and system include classifying scenes in the sequence of image frames, analyzing the content of the image frames and performing temporal filtering on the image frames. The method and system further include applying a set of rules to results of the classification and the content analysis to adapt characteristics of the temporal filtering for the scene.

Abstract: A phase shift mask having transmission properties that are dependent at least in part on an intensity of an incident light beam. The phase shift mask has a mask substrate that is substantially transparent to the incident light beam. A first phase shift layer is disposed on the mask substrate. The first phase shift layer has a refractive index that is nonlinear with the intensity of the incident light beam. The refractive index of the first phase shift layer changes with the intensity of the incident light beam on the phase shift mask. By using a first phase shift layer on the phase shift mask that has a refractive index that is non linear with the intensity of the incident light beam, properties of a light beam transmitted through the first phase shift layer, such as interference patterns in the transmitted light beam, can be adjusted by adjusting the intensity of the incident light beam.

Abstract: A method of silicon design reproducibility enhancement using priority assignments prior to performing a conventional optical proximity correction process on a device. The present invention seeks to improve the manufacturability of VLSI devices. The present invention inserts a priority assignment step prior to the conventional OPC correction process in order to assert better control over transistor parameters. The priority assignment step sorts the layout by degree of importance to the cell/device performance. Areas designated as critical are given higher priority values while areas designated as non-critical are given lower priority values. The present invention imposes more precise accuracy requirements to high priority value areas and less precise accuracy requirements to low priority value areas. As a result, the present invention imposes the tightest accuracy requirements to critical areas of device performance, rather than attempting to achieve overall accuracy during the OPC correction process.

Abstract: A method of optimizing a bond out design includes steps of: (a) receiving as input an initial bond out design including at least one selected I/O pad and a top redistribution layer; (b) determining whether to include a lower redistribution layer in an optimized bond out design; (c) selecting a trace design to be included in the optimized bond out design for connecting the selected I/O pad to the top redistribution layer according to a bump function of the selected I/O pad; and (d) generating as output the optimized bond out design.

Abstract: A method and computer program are disclosed for generating a hardware description language configuration from a generic phase locked loop architecture that include steps of: (a) receiving as input values for a set of configuration variables for a phase locked loop; (b) applying the values for the set of configuration variables to a generic top level model of the phase locked loop to generate a specific configuration of the phase locked loop from the generic top level model; and (c) generating as output a hardware description language code for the specific configuration of the phase locked loop.

Abstract: The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group III metal.

Abstract: The present invention is directed to a method and apparatus for mapping a customer memory onto a plurality of physical memories.

Abstract: An apparatus including a plurality of first base circuits, a plurality of second base circuits, a first test circuit, a second test circuit, and a test path. The plurality of first base circuits may be coupled to the plurality of second base circuits via one or more base circuit paths on a layout. The first test circuit may be disposed in a first distal location of the layout. The second test circuit may be disposed in a second distal location of the layout. The test path may be configured to (i) couple the first test circuit to the second test circuit and (ii) generate a test time delay from the first test circuit to the second test circuit incrementally longer than a maximum time delay generated by any of the base circuit paths.

Abstract: A method of noise analysis and correction of noise violations for an integrated circuit design includes steps of receiving as input a standard parasitic exchange file for an integrated circuit design and parsing the standard parasitic exchange file to generate a resistance graph. A representation of the resistance graph is generated to determine noise critical nets. A list is generated of only noise critical nets from the representation of the resistance graph. A net is selected from the list of only noise critical nets, and a value of total crosstalk noise in the selected net from all aggressor nets relative to the selected net is calculated. The value of total crosstalk noise in the selected net is generated as output for correcting a noise violation.

Abstract: A logical gate and a comparator are used to detect page boundaries in a data stream. A current address and a predetermined page size, that is an integer power of 2, are compared using a Boolean logic gate such as AND or XOR to detect a page boundary in a data stream. The output from the Boolean logic gate is compared to a predetermined value to cause a signal to be generated, indicating the end of the page.

Abstract: Methods and associated structure for providing broadcast of PCI bus transactions using device ID messaging (DIM) features of the PCI bus specifications. A vendor defined class of messages are defined using device ID messaging to provide broadcast of messages across PCI bus bridge devices to multiple PCI bus segments. One aspect hereof provides for using implicitly addressed device ID messaging such that bridge devices, compatible with the vendor defined message classes, will forward the message upstream and downstream. Another feature provides for use of explicitly addressed device ID messaging to effectuate the desired broadcast. Another aspect hereof provides for translation of a received DIM formatted message with broadcast information and applying the broadcast information to a second bus segment as a standard PCI broadcast transaction.

Abstract: For use in a floating-point unit that supports floating-point formats having fractional parts of varying widths and employs a datapath wider than the fractional parts, a circuit and method for normalizing and rounding floating-point results and processor incorporating the circuit or the method. In one embodiment, the circuit includes: (1) left-shift circuitry for aligning a fractional part of the floating-point result with a most significant bit of the datapath and irrespective of a width of the fractional part to yield a shifted fractional part and (2) rounding circuitry, coupled to the shift circuitry, that rounds the shifted fractional part.

Abstract: A method for generating a plurality of timing constraints for a circuit design is disclosed. The method generally includes the steps of (A) identifying a plurality of clock signals by analyzing the circuit design, (B) determining a plurality of relationships among the clock signals and (C) generating the timing constraints for the circuit design in response to the clock signals and the relationships.

Abstract: A method for determining outlier data points in. A subset of dataset patterns is selected from a set of mathematical dataset patterns, and the subset of dataset patterns is combined into a composite dataset. The composite dataset is compared to the dataset, and a degree of correlation between the composite dataset and the dataset is determined. Data points within the composite dataset are selectively weighted to improve the degree of correlation, and the steps described above are selectively iteratively repeated until the degree of correlation is at least a desired value. Residuals for the data points within the composite dataset are selectively determined. At least one of the weighted data points within the composite dataset that are weighted within a first specified range, and data points within the composite dataset that have a residual within a second specified range, are selectively output as outlier data points.

Abstract: A clock generating circuit for a pseudo dual port memory incorporates feedback, delays, and latches to ensure that the write (read) operation clock pulse is sufficiently spaced in time from the read (write) operation clock. The clock generating circuit receives an external clock, a read enable signal, a write enable signal, and a reset signal as inputs. Advantages include minimization of the clock cycle time and operation unaffected by the duty ratio of an external clock. Delay circuitry may be added such that the generated clock signal has sufficient fan out and is sufficiently stable.