Abstract: A method for providing a nonfunctional circuit design for evaluation in accordance with a static timing analysis is provided herein. The method initially generates a netlist, and then creates a standard delay format (SDF) file from the netlist. The standard delay format file contains occurrence names and delays associated with all elements of the design. The method subsequently selects elements of the design, alters the functionality of each selected element, and alters the standard delay format file entries corresponding to each selected element. The functional alteration of selected elements comprises altering an AND gate to be an OR gate, altering a NAND gate to be a NOR gate, altering an OR gate to be an AND gate, altering a NOR gate to be a NAND gate, altering an XOR to be an XNOR, and/or altering an XNOR to be an XOR in a predetermined manner.