Abstract: A semiconductor DRAM comprising a circuit arrangement in which an undesirable effect due to the coupling capacitance between bit lines thereof can be reduced, comprises: a plurality of bit lines arranged parallel to each other; a plurality of word lines intersecting each plurality of bit lines; a plurality of upper sense amplifiers respectively connected to uppermost ends of each of odd numbered bit line pairs; a plurality of lower sense amplifiers respectively connected to lowermost ends of each of even numbered bit line pairs; a memory cell array having a plurality of memory cells arranged sequentially in a diagonal line within selected locations of a plurality of spacings formed by intersection of the bit lines and word lines, the memory cell being disposed at every fourth spacing in a row and a column; first latching means for activating said upper sense amplifiers, the latching means being connected with said upper sense amplifiers; and second latching means coupled with said lower sense amplifiers, said