Abstract: An electronic component includes a component enclosure. At least one subcomponent is positioned within the component enclosure. The at least one subcomponent is configured to be thermally coupled to the component enclosure.

Abstract: A segmented subsystem, for use within an automated test platform, includes a first subsystem segment including a first data sequencer configured to coordinate the execution of one or more instructions within the first subsystem segment. A second subsystem segment includes a second data sequencer configured to coordinate the execution of one or more instructions within the second subsystem segment.

Abstract: A scalable test platform includes a PCIe-based event fabric. One or more instrument subsystems are coupled to the PCIe-based event fabric and configured to interface one or more devices under test and generate captured test data.

Abstract: A scalable test platform includes a PCIe-based event fabric. One or more CPU subsystems are coupled to the PCIe-based event fabric and configured to execute an automated test process. One or more instrument subsystems are coupled to the PCIe-based event fabric and configured to interface one or more devices under test.

Abstract: A method, computer program product, and computing system for, upon the occurrence of a computer-related event, comparing code utilized by one or more subsystems included within a scalable test platform to code available from a remote location. If the code available from the remote location is newer than the code utilized by one or more subsystems, the code available from the remote location is obtained, thus defining newer code. The code utilized by one or more subsystems is updated with the newer code.

Abstract: A segmented subsystem, for use within an automated test platform, includes a first subsystem segment configured to execute one or more instructions within the first subsystem segment. A second subsystem segment is configured to execute one or more instructions within the second subsystem segment. The first subsystem segment includes: a first functionality, a second functionality, and a status polling engine. The status polling engine is configured to: determine a first status for the first functionality and a second status for the second functionality, and generate a consolidated status indicator for the first subsystem segment based, at least in part, upon the first status for the first functionality and the second status for the second functionality.

Abstract: A high voltage connector assembly includes a plurality of pin assemblies, each of the plurality of pin assemblies having a first end and a second end. The first end of each of the plurality of pin assemblies is configured to releasably electrically engage a load board. A plurality of pin pads, wherein the second end of each of the plurality of pin assemblies is configured to electrically engage a pin pad included within the plurality of pin pads. A plurality of connector pads are electrically coupled to the plurality of pin pads, wherein each of the plurality of connector pads is configured to be electrically coupled to a wire-based conductor included within a plurality of wire-based conductors. A potting compound is configured to encapsulate the plurality of connector pads.

Abstract: A terminal end for a flat test probe having tapered cam surfaces providing a lead-in angle on the tail of the terminal end which extend to a sharp rear angle to engage detents or projections within a receptacle. The tapered cam surfaces and shape rear angles allow the probe to be inserted into the receptacle with minimal force to retain the flat test probe within the receptacle.

Abstract: A test fixture for testing loaded printed circuit boards having a plurality of test points having a probe plate including an array of widely spaced high force spring test probes in compliant contact with solid translator pins located in a translator fixture removably positioned over the probe plate. The test fixture includes optimization software wherein translation of the test signals are optimized by providing the shortest interconnect distance in the x-y plane between the test points on the printed circuit board and the test probes in the probe plate. The fixture further includes an unpowered opens device for testing components on the loaded printed circuit board.

Abstract: A method for identifying and reducing spurious frequency components is provided. A method in accordance with at least one embodiment of the present disclosure may include generating a digital sinusoidal waveform at a direct digital synthesizer (DDS) and receiving the digital sinusoidal waveform at an audio digital-to-analog converter. The method may further include converting the digital sinusoidal waveform to an analog sinusoidal waveform containing spurious frequency components, combining the analog sinusoidal waveform with an analog distortion correction waveform to generate a composite output waveform and receiving the composite output waveform at notch filter circuitry. The method may also include filtering the composite output waveform to generate a filtered composite output waveform and amplifying a difference between the filtered composite output waveform and a signal from a circuit-under-test (CUT) to generate an amplified analog signal.

Abstract: A method for identifying and reducing spurious frequency components is provided. A method in accordance with at least one embodiment of the present disclosure may include generating a digital sinusoidal waveform at a direct digital synthesizer (DDS) and receiving the digital sinusoidal waveform at an audio digital-to-analog converter. The method may further include converting the digital sinusoidal waveform to an analog sinusoidal waveform containing spurious frequency components, combining the analog sinusoidal waveform with an analog distortion correction waveform to generate a composite output waveform and receiving the composite output waveform at notch filter circuitry. The method may also include filtering the composite output waveform to generate a filtered composite output waveform and amplifying a difference between the filtered composite output waveform and a signal from a circuit-under-test (CUT) to generate an amplified analog signal.

Abstract: A method for identifying and reducing spurious frequency components is provided. A method in accordance with at least one embodiment of the present disclosure may include generating a digital sinusoidal waveform at a direct digital synthesizer (DDS) and receiving the digital sinusoidal waveform at an audio digital-to-analog converter. The method may further include converting the digital sinusoidal waveform to an analog sinusoidal waveform containing spurious frequency components, combining the analog sinusoidal waveform with an analog distortion correction waveform to generate a composite output waveform and receiving the composite output waveform at notch filter circuitry. The method may also include filtering the composite output waveform to generate a filtered composite output waveform and amplifying a difference between the filtered composite output waveform and a signal from a circuit-under-test (CUT) to generate an amplified analog signal.

Abstract: A method, circuit, and computer program product for receiving a first intermediate signal that is at least partially based upon a first reference signal. A second intermediate signal is received that is a time-shifted version of the first intermediate signal. An output signal is generated that is based upon the difference between the first intermediate signal and the second intermediate signal. An anticipated differential change in the output signal is determined, the anticipated differential change to occur based upon a transition in the first reference signal. A realized differential change in the output signal is measured, the realized differential change occurring based upon a transition in the first reference signal. The realized differential change in the output signal is compared to the anticipated differential change in the output signal to determine a nonlinearity indicator.