Abstract: The scaleable OFDM system according to the principles of the present invention provides increased flexibility and adaptability by providing scaling of the operating parameters and/or characteristics for the OFDM system. For example, control circuitry can scale the bit rate by scaling of the OFDM symbol duration, the number of carriers and/or the number of bits per symbol per carrier. Scaleability permits the scaleable OFDM system to operate in various communications environments requiring various operating parameters and/or characteristics. By scaling the operating parameters and/or characteristics of the OFDM system when control circuitry determines that different operating parameters and/or characteristics are necessary or advantageous, the control circuitry can dynamically change the operating parameters and/or characteristics, thereby providing compatibility or the desired performance.

Abstract: An integrated circuit, e.g. an AC '97 conforming audio codec, includes a digital filter and gain module including multiple channels of gain control and multiple channels of digital filtering. A gain control module includes an overflow check of data samples requiring differing lengths of clamping. Each channel of the digital filter includes a finite impulse response (FIR) filter, and an infinite impulse response (IIR) filter. The digital filtering is implemented largely in hardware independent of the number of channels required and/or independent of the required order of the filtering. Thus, filter channels can be added or additional filtering implemented merely by increasing the clock speed without changing the digital filter design. The FIR filter is capable of being reset each frame to prevent a DC buildup at internal nodes. The IIR filter performs a plurality of 2nd order biquadratic equations in an overall average of as few as four clock cycles per 2nd order biquad.

Abstract: A printed wiring board including a first solder mask covering a portion of a first conductor pad. The inner perimeter of the first solder mask extends radially inward of the outer perimeter of the first conductor pad so that a portion of the first connector pad proximate its outer perimeter is covered by the first solder mask. The inner perimeter of the first solder mask is radially outward of the inner perimeter of the first connector pad so that a portion of the first connector pad proximate the inner perimeter of the first connector pad is left exposed. In addition, the printed wiring board may include a second solder mask that covers a portion of a second connector pad. The second solder mask configured with respect to the second connector pad similar to that of the first solder mask with respect to the first connector pad. Alternatively, or in addition to the second connector pad, the printed wiring board may include a conductor path of which at least a portion is covered by a second solder mask.

Abstract: This invention relates to a system and method for economically locating an ESD event with a reasonable degree of accuracy. It performs this function using a binary approach in which one or more binary ESD locator boxes are used. Each of these binary ESD locator boxes incorporates two antennas and performs the function of determining which of these antennas receives the ESD signal first. This determination establishes the ESD event as occurring to one side of a planar surface. By incorporating one or more additional binary ESD locator boxes, the system can determine whether an ESD event occurred within a two dimensional area or within a three dimensional area.

Abstract: Memory test hardware is provided for generating signals for testing a first memory array and a second memory array. The first memory array and the second memory array may be any two of main memory array, a spare memory array, and reconfiguration memory array, or the apparatus may be adapted for testing all three memory arrays. The memory test hardware may include a controller for generating control signals, a data generator coupled to the controller for generating data signals, and an address generator coupled to the controller for generating address signals. The test device may further include an output data evaluator and repair unit for receiving signals from the main memory array and the spare memory array and for detecting faults in those arrays.

Abstract: An integrated circuit includes a memory cell that stores a data bit corresponding to one of a low and a high voltage. A memory element is coupled to a data node for storing the data bit and to an inverse data node for storing an inverse of the data bit. At least one write-access port has a write-access switch having an input terminal coupled to a data input line, an output terminal coupled to the data node, and a control terminal coupled to a write control line for switching the write-access switch on or off to provide a write-data bit from the data input line to the write-access port. A preset switch is employed which has a first terminal coupled to one of the data node and the inverse data node, a second terminal coupled to a voltage source sufficient to cause the data node to store a logic-1 data bit when the preset switch is on, and a preset control terminal for switching the preset switch on or off to preset the memory cell before a write operation is coupled to a preset control line.

Abstract: A feedforward linearizer includes a signal cancellation circuit and an error cancellation circuit. The signal cancellation circuit includes a tap delay line, that delay the input signal by a predetermined time delay so as to provide several delayed versions of the input signal. Each delayed version of the input signal is weighted by a tap coefficient. The weighted signals are then added together and fed to the power amplifier. The tap coefficients are derived such that the signals traveling through the upper and lower branch of the signal cancellation loop are aligned and that the output signal of the power amplifier is equalized.

Abstract: A multiplier contains an array of partial product generators, at least one new modified-Booth encoder. Corresponding to each new modified-Booth encoder, the partial product generator array includes a new adder cell. The partial product generator array receives inputs Y0 . . . YN with the Y0 receiving partial product generator being a new partial product generator for generating a partial product PP*(0,j). The new modified-Booth encoder receives multiplier bits and a multiplicand input Y0, and generates control signals and a carry in signal. The new adder cell is connected to the new modified-Booth encoder, the Y0 receiving new partial product generator and the (j−2) row Y2 receiving partial product generator and generates a partial product and an intermediate carry out signal so as to reduce the number of gate delay stages in the critical path of the multiplier.

Abstract: A method of training a TTS or other system to assign intonational features, such as intonational phrase boundaries, is described. The method of training involves taking a set of predetermined text (not speech or a signal representative of speech) and having a human annotate it with intonational feature annotations. This results in annotated text. Next, the structure of the set of predetermined text is analyzed to generate information. This information is used, along with the intonational feature annotations, to generate a statistical representation. The statistical representation may then be stored and repeatedly used to generate synthesized speech from new sets of input text without training the TTS system further.

Abstract: A door for an outdoor cabinet such as those used in telephony or CATV systems. The door has a first gasketed section to provide a first area of the cabinet with an airtight seal for protecting components housed therein from the outside environment. This first section of the door also includes a multi-point compression latch. The door has a second ungasketed section which ventilates gases around its unsealed perimeter from a second area of the cabinet housing batteries. This second section of the door includes a slam latch that is automatically engaged when the compression latch on the first door section is engaged.

Abstract: A wavelength division multiplexed optical system utilizes a plurality of lasers each operating at a different wavelength. Each laser is directly modulated with independent data at an NRZ signal of a given bit rate frequency and their outputs are combined as a train of pulses in a single optical fiber in the WDM format. The train of pulses is passed through a Mach-Zehender modulator driven with a sine wave synchronized with the bit rate of the NRZ drive to the lasers.

Abstract: A method for efficiently updating as shared data structure in a multiprocessor environment comprises accessing a queue variable associated with time-based data events in the data structure. Information associated with the queue variable is used to determine the point of insertion of a new time-based data event. If a new time based data event is inserted, the data of the queue variable of a preceding time-based data event is altered to identify the new time-based data event. An embodiment employing a contention-free locking mechanism is also disclosed.

Abstract: An optical mirror switch is formed by utilizing a pair of walk-off devices separated by a polarization switch. A first signal port is coupled to the first walk-off device and a second signal port is coupled to the second walk-off device. A reflective surface is also disposed beyond the output of the second walk-off device. In a first, “pass through” state of the switch, an optical signal applied as an input at the first signal port will propagate through the switch and exit at the second signal port. In a second, “reflective” state of the switch, an optical signal applied as an input at the first signal port will propagate through the switch, impinge the reflective surface and be re-directed back through the switch and exit through the first port. The “state” of the switch is controlled by the “state” of the polarization switch (which either exchanges the polarization states of the orthogonal components passing through, or maintains them).

Abstract: There is disclosed, a converter for converting an input signal from one form to another. The converter includes a slicing circuit adapted to slice a signal into levels. The slicing circuit includes at least one threshold for establishing slicing levels. Dither is employed to vary at least one slicing level in the slicing circuit.

Abstract: In accordance with the present invention, a communications system transmits a predetermined signal, from a first, sending, end of a communications system to a second, receiving, end of a communications system. The predetermined signal is distorted by the communication system and is received as a distorted signal that is compared to a known version of the originally transmitted signal. A comparison signal related to the difference between the originally transmitted signal (as represented by the known version of the originally transmitted signal) and the distorted predetermined signal as received at the receiving end is employed to adjust the transfer characteristic of a programmable converter to compensate for the distortion introduced by the communication system.

Abstract: The specification describes a Mach-Zehnder electro-optic modulator device in which the ridge containing the waveguides in the interactive electro-optic regions have re-entrant sidewalls. This shifts the peak in the RF field profile to below the surface of the ridge and closer to the peak of the optical field, thereby producing a device with reduced drive voltage.

Abstract: An acoustic signature recognition and identification system receives signals from a sensor placed on a designated piece of equipment. The acoustic data is digitized and processed, via a Fast Fourier Transform routine, to create a spectrogram image of frequency versus time. The spectrogram image is then normalized to permit acoustic pattern recognition regardless of the surrounding environment or magnitude of the acoustic signal. A feature extractor then detects, tracks and characterizes the lines which form the spectrogram. Specifically, the lines are detected via a KY process that is applied to each pixel in the line. A blob coloring process then groups spatially connected pixels into a single signal object. The harmonic content of the lines is then determined and compared with stored templates of known acoustic signatures to ascertain the type of machinery. An alert is then generated in response to the recognized and identified machinery.

Abstract: A system and method for translating a non-logic-family signal level into a logic-family signal level, the system comprising: a source of a non-logic-family signal that can assume a first and a second non-logic-family state; and a translator for determining whether the signal is in the first non-logic-family state, and if so, providing a translated signal having a first-logic family level. The translator can take the form of a comparator controlling an output transistor tied to a pull-up resistor, or a programmed processor. Examples of the logic-families include transistor-transistor logic (TTL) and complimentary metal oxide semiconductor (CMOS) logic. Examples of sources of non-logic-family signals includes a light emitting diode, a buzzer and a beeping device.

Abstract: A clamp for holding at least one laser component during a facet coating process. The clamp includes a first elongate member for contacting a first side of the laser component(s) and a second elongate member for contacting a second side of the laser component(s). The clamp also includes a magnetic member overlying a third side of the laser component(s), and at least one magnet disposed adjacent to the magnetic member, so that the magnetic member is drawn towards the third side of the laser component(s). The first and second elongate members, the magnetic member and the at least one magnet hold the laser component(s) therebetween.

Abstract: A retainer for a circuit board test probe includes a unitary member in which the test probe is inserted. The retainer may then be plugged into a desired opening in a test fixture plate, with a circumferential bead on the retainer and a circumferential groove in the plate opening providing a snap-in feature. Inward compression of the retainer moves the bead out of the groove to allow the retainer to be removed from the plate opening.