Abstract: Improved linearity in a line driver amplifier is realized by employing one or more amplifier sections each including an adaptive gain amplifier connected in parallel with a distributed gain amplifier. In an embodiment of the invention, first and second amplifier sections are connected in circuit relationship to an input and an output of the line driver amplifier to form a symmetrical amplifier configuration. In a specific embodiment of the invention, the adaptive gain amplifiers in each amplifier section are class AB type amplifiers and the distributed gain amplifiers in each amplifier section are class B amplifiers. Specifically, each of the distributed gain class B amplifiers each include a plurality of output transistors and a corresponding plurality of auxiliary amplifiers. The output transistor and auxiliary amplifier pairs are connected in parallel.

Abstract: A bond pad support structure is located beneath a bond pad on an integrated circuit. The bond pad support structure includes a first bond pad support layer at least partly located below the bond pad. The first bond pad support layer has a plurality of radial patterns with at least one space between the radial patterns. The radial patterns may be, for example, straight lines having approximately uniform thickness. Alternatively, the radial patterns may be triangles, each of which has an apex pointing to the center of a region below the bond pad. The radial patterns may have a plurality of different lengths. A second bond pad support layer is located on the first bond pad support layer. The second bond pad support layer fills at least a portion of the space between the radial patterns.

Abstract: A multiple agent system allowing each of a plurality of agents, i.e., processors, to present a different address, data, control and/or clock signals to a common shared synchronous memory. The signals from each of the agents is arbitrated in response to a memory access request to determine a winning agent. The address, data, control and clock signals to the shared synchronous memory are controlled so as to prevent undesirable high frequency waveforms and/or glitches from being presented to the shared synchronous memory during an arbitration period including a transition period between the previous owner's clock signal and the winning agent's clock signal. For instance, in the case of the clock signal, a clock switching control circuit disables the clock signal to the shared synchronous memory during the arbitration period for a period of time of at least about one phase of an arbiter clock signal before the transition period and one phase of the arbiter clock signal after the transition period.

Abstract: Compliant, resilient mounting means are provided for minimizing stresses on the platform of an optical sub-assembly package that tend to be caused by such factors as the mounting of the package base to a rigid, external platform, as by bolting, so as to maintain good alignment between the laser beam emitted from a laser chip mounted on the platform and the lens of an optical fiber also mounted on the platform.

Abstract: A slack storage bracket for use in fiber optic cable splice enclosures having a body, mounting members for mounting the slack storage bracket to the enclosure, and opposed radial shelf portions extending outwardly from the body to hold the cable slack. The shelf portions preferably have stops to keep the cable slack from slipping off of the shelf portions. The body of the bracket is preferably an arc which, like the radial shelf portions, have a radius of not less than the minimum bend radius of the cable to avoid damage to the cable.

Abstract: A wire-wrap connector block having a base that includes an articulable wall section that facilitates both automated wire-wrapping and potting procedures. During the wire-wrap procedure, the articulable wall section is latched in a position that permits the wire-wrap equipment to access the wire-wrap terminals without undesirable vertical movement of the wire-wrap equipment and wire. During the potting procedure, the articulable wall section is latched in a position in which the articulable wall section, together with another, non-articulable wall section, creates a substantially continuous wall about the bottom surface of the wire-wrap connector block base, defining a potting well or cavity within which potting material may be deposited.

Abstract: A method and device for obtaining a desired phase of optical characteristic of a Fabry-Perot (FP) etalon using multiple optical detectors which, while passively aligned at various positions relative to an incident light beam, detect different phases of light signal emerging from the FP etalon. An FP etalon and optical detector array constructed in accordance with the present invention may be used as a frequency discriminator in an optical system where the FP etalon optical characteristic is required to have a particular phase.

Abstract: A technique for preventing the user of a wireless terminal from carrying a wireless terminal into the umbra of a fade is disclosed. In particular, some embodiments of the present invention notify the user that the user is in danger of entering the umbra and assist the user in navigating from the fade. An illustrative embodiment of the present invention comprises: creating a first measurement of signal quality, SQ(n), of a signal received from a wireless terminal; and, when the first measurement of signal quality, SQ(n), is unsatisfactory, transmitting a first message to the wireless terminal to direct a user of the wireless terminal to move the wireless terminal in one direction.

Abstract: A method and apparatus for increasing system capacity in a mixed-rate wireless communication are disclosed. Improvements are obtained using multiuser detection or antenna array processing techniques or both to explicitly cancel or attenuate only the high power users. Multiuser detection may be combined with antenna array processing to recover capacity appropriated by the high-power users. By mitigating the interference effects of only the high-powered users, the computational burden is manageable. An antenna array algorithm or a multiuser detection algorithm or both, are applied only to n high rate users (n<k total users). In an antenna array processing implementation, fewer antennas may be employed (one for each high-rate user). In a multiuser detection implementation, fewer cancellation stages may be employed (one for each high-rate user).

Abstract: A fan module for use with an electronic equipment chassis having a fan bay contained therein. The fan module may comprise a fan assembly that is electrically connectable to a power source that is associated with the electronic equipment chassis and a mounting bracket that is configured to be removably received in the fan bay and configured to cradle and receive the fan assembly therein. The mounting bracket includes a latch assembly that is configured to cooperatively engage the fan bay and removably retain the fan module in the fan bay. Thus, the present invention provides a modular fan assembly and mounting bracket that can be easily inserted and removed from an electronic equipment chassis.

Abstract: Apparatus for implementing the application of duo-binary signal encoding in high-power, high-speed transmission systems which may be employed to mitigate the problem of stimulated Brillouin scattering. A dual-drive Mach-Zehnder interferometer modulator is used, with data being applied to both modulation inputs. The voltage difference between the two modulation inputs is between −V&pgr; and +V&pgr;. In one embodiment, the data signal is applied to one input, and the same signal, delayed by one bit, is applied to the second input, and the modulator is biased so as to have minimum throughput when both inputs are identical. In the second embodiment, the data signal is applied to one input and the complementary data-bar signal, delayed one bit, is applied to the second input, with the modulator biased to minimum throughput when both inputs are identical. This novel implementation has been verified experimentally showing a power penalty of less than 1 dB relative to a conventional binary signal.

Abstract: An attenuator element for use between two optical fiber connector ferrules comprising an optical member having an outer periphery, a neck portion connected to the outer periphery of the optical member, a head portion connected to the neck portion, and a severable grip having a substantially planar body portion and a wedge portion attached to the body portion. The attenuator element can be manually manipulated by grasping the grip and placing the optical member in an appropriate apparatus at which point the grip can be manually broken off of the attenuator element. Typically, the grip is used to place the optical member of the attenuator element in a ferrule sleeve of a buildout system.

Abstract: A unitary two-section semiconductor optical amplifier including a first active region, a second active region, and a passive region integrally connected between the first and second active regions to minimize optical loss therebetween. The arrangement of the two-section semiconductor optical amplifier is advantageous in that the gain in the first active region may be increased in order to maintain a substantially constant input power level to the second active region over a relatively wide dynamic range of input power levels to the first active region.

Abstract: A fixture and method for providing accurate and repeatable alignment and attachment of a semiconductor wafer to a corner cube exposure fixture includes a vacuum-assisted wafer holder of rectangular shape. The wafer holder is first placed upon an L-shaped loading fixture so that a wafer may be positioned against the front surface of the holder and manipulated until the pair of wafer flats abut each leg of the L-shaped fixture. When so aligned, a vacuum is applied to secure the attachment and alignment of the wafer vis-à-vis the wafer holder. The wafer holder is thereafter inserted in a corner cube exposure fixture, where the fixture is formed to include a right-angle bracket with alignment features formed in one leg of the angle. The wafer holder also includes alignment features in its bottom surface, where these features are formed to mate with the bracket upon attachment.

Abstract: An integrated circuit has a memory array comprising memory devices formed in a multiplicity of electrically isolated semiconductor regions that share a common set of bit lines. A given semiconductor region, typically a tub, is biased to a given voltage if a memory cell formed in that tub is accessed for a write operation, and biased to another voltage at other times. Although there may be many memory devices along the same bit line, during programming only the memory devices in the selected tub will be disturbed by the tub bias. Other memory devices residing in unselected tubs are protected against the bit line disturb. The present technique is especially advantageous when used with flash EEPROM memory cells that utilize secondary electron injection to assist in programming the cells.

Abstract: A process sequence for forming a semiconductor device utilizes a passivation annealing process using deuterium which enhances immunity to hot carrier effects and extends device lifetime. The process sequence is carried out prior to the introduction of metal conductive films to the device. The process sequence includes a three-step passivation, de-passivation, re-passivation sequence and utilizes a barrier film to encapsulate deuterium molecules in the vicinity of a gate oxide, during the de-passivation operation.

Abstract: An automated system for electroless metallization of optical glass fibers, includes a plurality of spaced apart plating stations having different solutions for electroless metallization of optical fibers. A motor-driven fiber transport and dipping apparatus is used in the system for shuttling optical glass fibers to the plating stations and immersing the optical glass fibers in the solutions. A programmable controller directs the transport and dipping apparatus to the plating stations in a selected order and at selected time intervals, and directs the apparatus at each of the stations to immerse the fibers into the solutions at a selected entry rate, for a selected duration, and at a selected withdrawal rate.

Abstract: A packaged microelectromechanical device having a housing with a plurality of ports. A bundle of a plurality of optical fibers is mounted in one of the plurality of ports by a welded or brazed flange. An array-type microelectromechanical device is mounted in another port of the housing by a welded or brazed flange and includes a plurality of elements adapted for interacting with the plurality of optical fibers, whereby information may be transmitted into the housing via one of the optical fibers and may be transferred out of the housing via another of the optical fibers. The array-type microelectromechanical device has a plurality of electrical control pins protruding outside the housing. A pair of windows in the housing provides ports for optical sensory signals for the array-type microelectromechanical device. Two conduits for providing pressurized inert gas are mounted in the housing by welded or brazed flanges.

Abstract: The present invention provides, in one embodiment, a battery container. In this particular embodiment, the container comprises a housing having side walls and a spacing ridge formed in and extending outwardly from the side walls. The spacing ridge forms a groove on an interior surface of the walls and has a slot formed in the spacing ridge at first and second opposing ends of the housing. In an alternate embodiment, the spacing ridge has a plurality of slots formed on opposing ends of the container. Typically, two adjacent slots are formed on each end such that opposing ends of the handle may engage the retaining pin through the slots. The container further comprises a handle and a retaining pin configured to be received within the interior groove adjacent the slot. The handle is cooperatively engageable with the retaining pin to provide a lifting point for the container when the retaining pin is received in the interior groove.

Abstract: A 16B/18B low disparity code is described. The 16-bit input word is split into two bytes, i.e., into two 8-bit words, and each byte is mapped to a 9-bit word. The image of each input byte under the mapping depends at least in part on its disparity, and also in some cases on the disparity of the other word. Certain of the images under the mapping are then inverted. The decision whether to invert an image depends, at least in part, on the running digital sum (RDS) of the output. The RDS is the sum of all 1's in the data stream from its beginning (or from a designated starting point). Significantly, all possible input words are grouped, by disparity, into four categories. The rule for mapping of input words is different for each of the four categories.