Abstract: A computer system includes a processor and bus logic, a decode logic circuit for the processor and bus logic access, a memory subsystem and at least one output port. Writes by the processor and bus logic to an output port also update corresponding location in memory through the decode logic. In one arrangement, a logical "OR" gate enables the memory in response to an output of the decode logic for activating the memory subsystem or an output of the decode logic for activating the output port.
Abstract: A Multiprocessor system is disclosed which includes a master processor, slave processor, and first and a second bank of memory for storing information to be operated on by the slave processor and a switch controlled by a master processor to switch the functional position of two banks of memory so that the slave processor switches from operating on information stored in the first bank to operating on information stored in the second bank and back under the control of the master processor.
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