Abstract: A synchronous digital system is disclosed which includes a system clock, a first and a second subsystem, each having a clock input, and a circuit for disabling the clock input to the second subsystem on a regular basis. The effective clock rate of the second subsystem is a fraction of the effective clock rate of the first subsystem.
Type:
Grant
Filed:
November 13, 1989
Date of Patent:
May 26, 1992
Assignee:
Lucid, Inc. (formerly Portable Computer)