Abstract: The present disclosure relates to a synaptic weight training method, a target identification method, an electronic device and a storage medium. The synaptic weight training method includes: inputting spike signals corresponding to training samples into a spiking neural network to be trained; learning a target synaptic weight in the spiking neural network with a back propagation rule to obtain a first branch weight; and learning the target synaptic weight with a synaptic plasticity rule to obtain a second branch weight; and updating the target synaptic weight according to the first branch weight and the second branch weight.

Abstract: Provided is a method for training spiking neuron network, including: inputting a spiking signal corresponding to a training sample into a spiking neuron network to be trained; and training the spiking neuron network based on a back propagation rule, wherein a forward propagation stage of training includes: adjusting a spiking firing threshold corresponding to a target layer in the spiking neuron network according to confidence corresponding to the target layer. Also provided are a method for processing data based on a spiking neuron network, an electronic device, and a non-transitory computer-readable medium.

Abstract: A computing core circuit, including: an encoding module, a route sending module, and a control module, wherein the control module is configured to control the encoding module to perform encoding processing on a pulse sequence determined by pulses of at least one neuron in a current computing core to be transmitted, so as to obtain an encoded pulse sequence, and control the route sending module to determine a corresponding route packet according to the encoded pulse sequence, so as to send the route packet. The present disclosure further provides a data processing method, a chip, a board, an electronic device, and a computer-readable storage medium.

Abstract: The present disclosure provides a signal transmission method and a signal transmission device, which are applied to a digital circuit including a plurality of circuit modules connected in series, and each circuit module is configured to perform corresponding operation processing based on a first clock signal provided by a first clock. The method includes: under driving of a second clock signal provided by a second clock, transmitting a first signal output by a current circuit module to a target circuit module in response to reception of the first signal, the first signal is a signal output by the current circuit module when operating based on the first clock signal, transmission of the first signal is completed within a current clock cycle of the first clock, and a clock rate of the second clock is greater than that of the first clock.

Abstract: Provided in the present disclosure are a data processing method and apparatus, and an electronic device, the method includes: determining a plurality of candidate data pieces, where the candidate data pieces are provided from corresponding data sources; and determining a target data piece based on priorities of the data sources corresponding to the plurality of candidate data pieces in a current cycle, wherein a same data source has different priorities in different processing cycles, and priority sequence numbers of a same data source in different processing cycles satisfy a nonlinear relationship.

Abstract: The present disclosure belongs to the technical field of machine learning. Specifically provided is a neural network model, including at least one intermediate layer including different types of neurons which correspond to different types of neural networks. The neural network model is obtained based on an initial neural network and a multi-valued mask during a training process, and the multi-valued mask is obtained by means of performing multi-value processing on a continuous mask. Further provided are a method for training neural network model, a time sequence data processing method, an electronic device, and a readable medium.

Abstract: The present disclosure provides a data transmission method and device for a network on chip and an electronic apparatus. The method includes: receiving, by a second network node, a first data packet sent by a first network node, the first data packet including first identification information and a data packet payload; determining, by the second network node, valid transmission information and second identification information corresponding to the valid transmission information according to the first identification information; determining, by the second network node, a second data packet according to the second identification information and the data packet payload; and sending, by the second network node, the second data packet according to the valid transmission information.

Abstract: A calibration method, a calibration apparatus, a terminal device and a storage medium are provided. The method comprises the following steps: determining layer attribute information of each to-be-calibrated layer in a model (S110); and determining the group in which each of the to-be-calibrated layers is located according to the total available resources and the layer attribute information of each of the to-be-calibrated layers (S120). The layer attribute information of any of the to-be-calibrated layers comprises layer required resources, the layer required resources are resources needing to be occupied when the to-be-calibrated layer is calibrated; and the total available resources are the total resources used for calibration.

Abstract: An embodiment of the present disclosure provides a weight precision configuration method, including: determining a pre-trained preset neural network including a plurality of layers each having a preset weight precision; reducing, based on a current threshold, the weight precision of at least one layer in the preset neural network to obtain a corrected neural network having a recognition rate greater than the current threshold; and reducing the weight precision of a layer includes: adjusting the weight precision of the layer; setting, if a termination condition is met, the weight precision of the layer to a corrected weight precision that is less than or equal to the preset weight precision of the layer; and returning, if the termination condition is not met, to the operation of adjusting the weight precision of the layer; and determining a final weight precision of each layer to obtain a final neural network.

Abstract: Disclosed are a network accuracy quantification method, system, and device, an electronic device and a readable medium, which are applicable to a many-core chip. The method includes: determining a reference accuracy according to a total core resource number of the many-core chip and the number of core resources required by each network to be quantified, with the number of the core resources required by each network to be quantified being the number of the core resources which is determined after each network to be quantified is quantified; and determining a target accuracy corresponding to each network to be quantified according to the reference accuracy and the total core resource number of the many-core chip.

Abstract: The present disclosure provides a method for converting numerical values into spikes. The method includes: generating an initial spike sequence according to input numerical values, where the initial spike sequence includes at least one data string, each of which is independently selected from one of a consecutive spike train or a consecutive non-spike train, the number of spikes in all of the at least one data string is equal to an expected value of the number of spikes in a target spike sequence to be generated, and the target spike sequence to be generated is a spike sequence of a spiking neural network within a time period; and randomly selecting and modifying data from the initial spike sequence, so as to form the target spike sequence. The present disclosure further provides an apparatus for converting numerical values into spikes, an electronic device, and a computer-readable storage medium.

Abstract: A neural network mapping method and a neural network mapping apparatus are provided. The method includes: mapping a calculation task for a preset feature map of each network layer in a plurality of network layers in a convolutional neural network to at least one processing element of a chip; acquiring the number of phases needed by a plurality of processing elements in the chip for completing the calculation tasks, and performing a first stage of balancing on the number of phases of the plurality of processing elements; and based on the number of the phases of the plurality of processing elements obtained after the first stage of balancing, mapping the calculation task for the preset feature map of each network layer in the plurality of network layers in the convolutional neural network to at least one processing element of the chip subjected to the first stage of balancing.

Abstract: A video retrieval method and apparatus, a device and a storage medium are provided. The method comprises the following steps: acquiring a comparison video clip from a video library according to the duration of a to-be-tested video (S110); determining the similarity between the to-be-tested video and the comparison video clip by a target spatio-temporal neural network, a spatio-temporal convolutional layer of the target spatio-temporal neural network being configured to be capable of performing two-dimensional convolution and temporal dimension information processing, respectively (S120); and traversing the video library, and outputting a retrieval result according to the similarity (S130).

Abstract: The disclosed method is applicable to a many-core system. The method includes: acquiring multiple pieces of .routing information, each of which includes two logical nodes and a data transmission amount between the two logical nodes; determining a piece of unprocessed routing information with a maximum data transmission amount as current routing information; mapping each unlocked logical node of the current routing information to one unlocked processing node, and locking the mapped logical node and processing node, wherein if there is an unlocked edge processing node, the unlocked logical node is mapped to the unlocked edge processing node; and returning, if there is at least one unlocked logical node, to the step of determining the piece of unprocessed routing information with the maximum data transmission amount as the current routing information.

Abstract: The present disclosure provides a brain-like computing chip and a computing device. The brain-like computing chip includes is a many-core system composed of one or more functional cores, and data transmission is performed between the functional cores by means of a network-on-chip. The functional core includes at least one neuron processor configured to compute various neuron models, and at least one coprocessor coupled to the neuron processor and configured to perform an integral operation and/or a multiply-add-type operation; and the neuron processor is capable of calling the coprocessor to perform the multiply-add-type operation.

Abstract: The present application provides a method and a device for controlling a storage format of an on-chip storage resource, the method for controlling the storage format of the on-chip storage resource includes: while mapping a neural network model to a many-core system, generating an on-chip storage resource of each processing core in the many-core system, and storing the on-chip storage resource into a specified file; and parsing out a storage format of the on-chip storage resource based on the specified file, obtaining occupied storage space of each processing core, and adjusting the storage format of the on-chip storage resource of each processing core based on the occupied storage space of each processing core.

Abstract: Provided are a path creation method and device for a network on chip and electronic apparatus. The method includes: receiving, by a second network node, a first data packet sent by a first network node, the first data packet carrying first idle address identification information, a destination network node address and path creation identification information, the first idle address identification information indicating a first idle position in a first path routing table of the first network node, the path creation identification information indicating a creation of a path; storing, by the second network node, the first idle address identification information in a second idle position in its second path routing table, and determining second idle address identification information; determining, by the second network node, a second data packet according to the second idle address identification information; and sending, by the second network node, the second data packet.

Abstract: Embodiments of the present disclosure provide multitask parallel processing method and apparatus, a computer device and a storage medium. The method is applied to a neural network consisting of a plurality of nodes, the neural network including at least one closed-loop path, and the method includes: inputting a data sequence to be computed into the neural network in a form of data packets, each of the data packets including multiple pieces of data; and computing, by the nodes in the closed-loop path, all the data in a currently received data packet each time a computation flow is started.