Abstract: A signal processing system and method is disclosed, applicable to environment providing voltage to Class-H driver. When using the signal processing system, the first is to detect the volume change of inputted voice and use the detection result as a power source to generate an expectation value for the circuit; the input end of the power generation circuit also adds a voltage offset in addition to the expectation value, so that the output voltage from the output end of the power generator provided to the Class-H driver is higher than a fixed value. The signal processing system and method of the present invention can adjust automatically and rapidly the output voltage signal for the power voltage provided to the Class-H driver by using negative feedback controller (such as, negative feedback loop, voltage offset and proportional integral differential (PID)) based on the detected volume change of inputted voice.

Abstract: The invention disclosed a signal processing system and method thereof, applicable to an environment providing accurate output frequency. By using the signal processing system, the stable output voltage (AMP OUT) of the error amplifier is inputted to the input of the voltage controlled oscillator (VCO), the output frequency (Fvco) of the VCO is provided to the input of fractional-N frequency divider for digital division. The output of the fractional-N frequency divider (Fo) is provided to the input of the frequency to voltage converter for frequency/voltage conversion. Then, the low pass filter is used to filter out the ripple of the output voltage (V1) of the frequency to voltage converter and the trebling jitter of the output of the fractional-N frequency divider. The signal processing system of the present invention utilizes the voltage locked loop property and digital frequency division to achieve accurate frequency output.

Abstract: A time clock signal processing system and method thereof, applicable to an environment of USB synchronous mode audio clock reconstruction, is disclosed. The clock signal processing method employed by the clock signal processing system first uses a first-stage phase-locked loops (PLL) to raise the frequency of the inputted USB start-of-frame (SOF) field, provides clock synchronization and outputs the second-stage PLL; then, the second-stage PLL reduces the timing jitter of the output of the first-stage PLL to below 20 ps.

Abstract: A recharging cable is disclosed, applicable to a smart recharging environment capable of self-detection and self-diagnosis, comprising: a cable; a plug, coupled to the cable, and having at least a power line set, and at least a communication line set, the at least power line set having a power line and a ground line, and the at least communication line set providing real-time communication between the recharging cable and a charging control end and a charged end; an electronic chip, located at one of the cable and the plug, the electronic chip being able to detect real-time information of the material property and device property at the charged end to estimate a real-time impedance information of the cable, and in combination with a historic impedance changes of the cable, to estimate an impedance reflection point of the cable related to ageing.

Abstract: A signal processing system and a method thereof are disclosed, using a differential amplifier to extract sensed signals associated with headphone wear status generated by the diaphragm of a headphone and transmitted to a sense ADC for digitization. To exclude residual music signal in the extracted sensed signals for subsequent processing, a temporary memory is provided to match and synchronize a round-trip delay in the signal processing system. The round-trip delay is computed to adjust the depth and clock speed of a buffer/FIFO of the temporary memory to eliminate residual music signal in order to separate the sensed signal of the headphone unit diaphragm displacement and use the extracted sensed signal as a reference source for subsequent analysis and auto-control and/or signal compensation.

Abstract: A USB controller with automatic clock generation comprising: an oscillating generator is used for generating an initial clock; a first phase locked loop is used for receiving the initial clock and outputting a controller operating clock having a first frequency; a controller is used for detecting at least one universal serial bus device and outputting an initial frame signal having a second frequency; a second phase lock loop is used for receiving the initial frame signal and outputting a sync frame signal having the first frequency; a third phase lock loop for receiving the sync frame signal and outputting a stabilizing frame signal having the first frequency; and a multiplexer is used for receiving the controller operating clock and the stabilizing frame signal and transmitting the controller operating clock or the stabilizing frame signals to the controller.

Abstract: A signal processing system and a method thereof are disclosed, using a differential amplifier to extract the sensed signals associated with the headphones wear status generated by the diaphragm of the headphone and push back to the sense ADC for digitization. Because the differential amplifier is non-ideal, certain residual music signal will exist. To exclude residual music signal for subsequent processing, a temporary memory is provided to match and synchronize the original playback signal retainment and the round-trip delay of external signal. The round-trip delay is computed to adjust the depth and clock speed of the buffer/FIFO of the temporary memory to, after synchronized with the total external propagation delay, eliminate residual music signal in a function block in order to separate the sense signal of the headphone driver unit diaphragm displacement and use the extracted sense signal for subsequent analysis and auto-control and/or signal compensation reference source.