Abstract: An inference task is performed using a computation device having a plurality of processing elements operable in parallel and connected via a connectivity system. Performing the task includes accepting at the device a specification of at least part of the inference task. The specification characterizes a plurality of variables and a plurality of factors, each factor being associated with a subset of the variables. Each of the processing elements is configured with data defining one or more of the plurality of factors. At each of the processing elements, computation associated with one of the factors is performed concurrently with other of the processing elements performing computation associated with different ones of the factors. Messages are exchanged via a connectivity system. The messages provide inputs and/or outputs to the processing elements for the computations associated with the factors and provide a result of performing of the at least the part of the inference task.

Abstract: An approach to converting an analog value based on a partition of an input range produces probabilities that the input is found within each of the regions based, for example, on a noisy version of the input. In some examples, iterative and/or pipelined application of comparison circuitry is used to accumulate a set of analog representations of the output probabilities. The circuitry can be adapted or configured according to the characteristics of the degradation (e.g., according to the variance of an additive noise) and/or prior information about the distribution of the clean input (e.g., a distribution over a discrete set of exemplar values, uniformly distributed etc.).

Abstract: Circuitry for stochastic computation includes processing nodes, including a first processing node and a second processing node, each configured to process an outcome stream having a plurality of outcomes, each outcome being in one of a plurality of states, wherein an outcome from said outcome stream is in a particular state with a particular probability; communication links configured to transmit outcome streams between pairs of said processing nodes; and a delay module on each of said communication links, said delay module configured to delay outcome streams traversing said communication link by an assigned delay; wherein said first and second processing nodes are connected by a plurality of data paths, at least one of which comprises a plurality of communication links, each of said data paths causing an aggregate delay to an outcome stream traversing said data path; wherein no two aggregate delays impose the same delay on an outcome stream.

Abstract: A processor implements a network of functional nodes and communication paths between the nodes. The processor includes a plurality of circuit implementations of the functional nodes of the processor; and a plurality of signal paths implementing the communication paths linking the circuit implementations of the nodes. At least some of the signal paths are configured to pass signal values represented according to temporal patterns of signal levels on the signal paths. The processor also includes a plurality of circuit components for conversion between a signal value represented as a signal level (e.g., voltage or current level) and a signal value represented as a temporal pattern.

Abstract: A circuit includes a signal processing circuit for accepting an input and for generating a set of outputs. The input is provided in an input range that has a set of representative values, and each output represents a measure of an association of the input with one or more of the representative values. The signal processing circuit includes a group of output sections, each output section being responsive to the input of the signal processing circuit. Each output section includes one or more sigmoid generators. Each sigmoid generator is responsive to an input of the output section to generate an output that represents a sigmoid function of the input of the output section. Each output section also includes a circuitry for combining the outputs of the one or more sigmoid generators to form one of the set of outputs of the signal processing circuit. An input transformation circuit is coupled to the plurality of output sections.

Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.

Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.

Abstract: Some general aspects relate to systems and methods of analog computation using numerical representation with uncertainty. For example, a specification of a group of variables is accepted, with each variable having a set of at least N possible values. The group of variables satisfies a set of one or more constraints, and each variable is specified as a decomposition into a group of constituents, with each constituent having a set of M (e.g., M<N) possible constituent values that can be determined based on the variable values. The method also includes forming a specification for configuring a computing device that implements a network representation of the constraints based on the specification of the group of variables. The network representation includes a first set of nodes corresponding to the groups of constituents, a second set of nodes corresponding to the set of constraints, and interconnections between the first and the second sets of nodes for passing continuous-valued data.

Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.

Abstract: Some general aspects of the invention relate to a circuit and to a method for analog computation, for example, using switched capacitor integrated circuits. In some examples, a circuit includes a first group of capacitors and a second group of capacitors that may store charges during circuit operation. The first and/or the second group of capacitors may include multiple disjoint subsets of capacitors. An input circuit is provided for receiving a set of input signals and for inducing a charge on each of some or all capacitors in the first group of capacitors according to a corresponding input signal. Switches, for example, transistors controlled by a sequence of clock signals, are used to couple different sets of capacitors. Different configurations of the switches are used to form different sets of the capacitors among which charge can redistribute.