Abstract: A flexible, modular communications processor is disclosed comprised of a plurality of microprocessors. A demand assigned bus is provided to couple the microprocessors through an arbitrator to an information storage and retrieval device. Each of the microprocessors comprises a conventional integrated circuit microprocessor, associated local memory, transmitters and receivers for coupling information to and from the bus and bus access circuitry, cooperating with the arbitrator to allocate the bus resource. Communication input/output is handled by a plurality of microprocessors configured as line processors, each coupled to its associated interface switch, which, in turn, is coupled to modems or other input/output devices. A background or executive microprocessor is included to manage system configuration and react to failures.