Abstract: The present disclosure set forth a method for a node to participate in an ad hoc network. The first node receives a first link information broadcasted omnidirectionally by a second node. The first link information indicates if the second node is communicating via a first directional link in a first polarization with a third node. The first node establishes a second directional link in a second polarization with the second node.

Abstract: A method for wavelet based data compression comprising: receiving data associated, with a set of pixels, computing wavelet coefficients by applying a series of Discrete Wavelet Transform (DWT) low-pass and high-pass filtering operations, wherein a number of filtering operations is reduced by: identifying common partial products for at least one of the lowpass filtering operations and the high-pass filtering operations, classifying a first portion of the wavelet coefficients as low magnitude coefficients and a second portion of the wavelet coefficients as high magnitude coefficients, eliminating the common partial products for the high magnitude wavelet coefficients, replacing multiplication operations for the low magnitude wavelet coefficients with shift-and-add operations, and eliminating the common partial products, and applying the DWT based on remaining filtering operations.

Abstract: A method and apparatus for direct digital synthesis (DDS) of signals using Taylor series expansion is provided. The DDS may include a modified phase-to-amplitude converter that includes read-only-memories (ROMs), registers and, a single size, such as a coarse, intermediate, and fine ROM corresponding to respective higher resolution phase angles. The outputs of the ROMs when combined can form a digital output signal in the form of a Taylor series of a sinusoid function.

Abstract: A method and apparatus for direct digital synthesis (DDS) of signals using Taylor series expansion is provided. The DDS may include a modified phase-to-amplitude converter that includes read-only-memories (ROMs), registers and, a single adder. Values stored in the ROMs may produce one component of a sinusoid signal, and each of the ROMs may be of a different size, such as a coarse, intermediate, and fine ROM corresponding to respective higher resolution phase angles. The outputs of the ROMs when combined can form a digital output signal in the form of a Taylor series expansion of a sinusoid function.

Abstract: In an illustrative embodiment, a data interface circuit is provided. The data interface circuit comprises data sources, input blocks, a space switch, output blocks and a multi-core processor. The data interface circuit allows data provided in different voltage ranges and sampling frequencies to be transmitted to the appropriate core in the multi-core processor via the switch. Data conversion elements in the input blocks convert data from the data sources and having varying voltage ranges and sampling frequencies into data having a voltage range and sampling frequency suitable for the space switch. Analogously, data conversion elements in the output blocks convert data from the space switch into data having a voltage range and sampling frequency suitable for the corresponding core in the multi-core processor. In one embodiment, level shifters and FIFO buffers are used in the input blocks and output blocks.

Abstract: In an illustrative embodiment, a data interface circuit is provided. The data interface circuit comprises data sources, input blocks, a space switch, output blocks and a multi-core processor. The data interface circuit allows data provided in different voltage ranges and sampling frequencies to be transmitted to the appropriate core in the multi-core processor via the switch. Data conversion elements in the input blocks convert data from the data sources and having varying voltage ranges and sampling frequencies into data having a voltage range and sampling frequency suitable for the space switch. Analogously, data conversion elements in the output blocks convert data from the space switch into data having a voltage range and sampling frequency suitable for the corresponding core in the multi-core processor. In one embodiment, level shifters and FIFO buffers are used in the input blocks and output blocks.

Abstract: A method for wavelet based data compression comprising: receiving data associated, with a set of pixels, computing wavelet coefficients by applying a series of Discrete Wavelet Transform (DWT) low-pass and high-pass filtering operations, wherein a number of filtering operations is reduced by: identifying common partial products for at least one of the lowpass filtering operations and the high-pass filtering operations, classifying a first portion of the wavelet coefficients as low magnitude coefficients and a second portion of the wavelet coefficients as high magnitude coefficients, eliminating the common partial products for the high magnitude wavelet coefficients, replacing multiplication operations for the low magnitude wavelet coefficients with shift-and-add operations, and eliminating the common partial products, and applying the DWT based on remaining filtering operations.

Abstract: A method and apparatus for direct digital synthesis (DDS) of signals using Taylor series expansion is provided. The DDS may include a modified phase-to-amplitude converter that includes read-only-memories (ROMs), registers and, a single adder. Values stored in the ROMs may produce one component of a sinusoid signal, and each of the ROMs may be of a different size, such as a coarse, intermediate, and fine ROM corresponding to respective higher resolution phase angles. The outputs of the ROMs when combined can form a digital output signal in the form of a Taylor series expansion of a sinusoid function.

Abstract: The present disclosure set forth a method for a node to participate in an ad hoc network. The first node receives a first link information broadcasted omnidirectionally by a second node. The first link information indicates if the second node is communicating via a first directional link in a first polarization with a third node. The first node establishes a second directional link in a second polarization with the second node.