Abstract: An electronic device includes a shift register including two or more cascaded memory cells configured to store respective data bits, and a sequencing circuit. At least a memory cell among the memory cells includes a data input for shifting a data bit from a previous memory cell in the shift register, a shift input for controlling the shifting of the data bit from the previous memory cell in the shift register, a data output for shifting a data bit to a next memory cell in the shift register, and an erase signal input for erasing the data bit stored in the memory cell prior to the shifting. The sequencing circuit is configured to shift data bits in the shift register by applying a sequence of erasure signals to erase inputs of the memory cells, and a sequence of shift signals to the shift inputs of the memory cells.