Abstract: A removable scraper device is described herein. The removable scraper device includes an attachment element and a socket defined by the attachment element, wherein the socket is configured to receive a post of a scraper element therein. The removable scraper device further includes a slot defined by the attachment element, wherein the slot is configured to receive a portion of a bucket of a wheeled-machine therein. The removable scraper device further includes an aperture defined by the attachment element and a bolt sized to be received within the aperture. In some embodiments of the removable scraper device, the bolt and aperture are configured to selectively press the attachment element against the bucket to removably secure the removable scraper device thereto.

Abstract: Embodiments of programmable delay line circuits are disclosed herein. The delay line circuit may comprise a first multiplexer having a first input coupled with an input line; a second multiplexer having a first input, and a second input coupled with an output of the first multiplexer, and an output coupled with a second input of the first multiplexer; a third multiplexer having a first input coupled with the output of the second multiplexer, a second input coupled with the input line, and an output coupled with an output line; a first control gate coupled with the third multiplexer to control the third multiplexer; and a second control gate coupled with the second multiplexer to control the second multiplexer; wherein the first and second control gates selectively control the second and third multiplexer, responsive to a delay value encoded in Gray Code.

Abstract: Embodiments provide systems, methods, and integrated circuits having a calibration structure with a calibration component and a measurement structure coupled to the calibration component. The measurement structure is configured to vary a current through the calibration component until a voltage of the calibration component equals an operation voltage. The variable current is a function of at least the operation voltage and a resistance of a resistor external to the measurement structure.

Abstract: Embodiments of crossbar devices constructed with Micro-Electro-Mechanical Systems (MEMS) switches are disclosed herein. A crossbar device may comprise m input terminals, n output terminals, n control lines and m×n MEMS switches coupled to the n control lines to selectively couple the m input terminals to the n output terminal. Each of the MEMS switches may comprise a contact node coupled to one of the m input terminals, a cantilever coupled to one of the n output terminals, a control node coupled to one of the n control lines to electrostatically control the cantilever to contact the contact node or be away from the contact node using electrostatic attractive or repulsive force respectively. The cantilever and the contact node are configured to remain in contact by molecular adhesion force, after the cantilever has been electrostatically controlled to contact the contact node, and the electrostatic attractive force has been removed. Other embodiments may be described and claimed.

Abstract: Embodiments provide crossbar structures, and reconfigurable circuits that contain crossbar structures, that include n inputs and an output, where n is an integer, chains of transistors coupled to the n inputs and the output, a plurality of control signal elements—each coupled to one or more transistors of the plurality of chains of transistors to selectively couple said n inputs to the output—and an additional chain of transistors coupled to at least some of the plurality of control signal elements and the output to selectively couple a constant output voltage to the output. Other embodiments may be disclosed and claimed.

Abstract: Embodiments provide methods, systems, and apparatuses including combinatorial or reconfigurable circuitry having input/output (I/O) circuitry with an I/O terminal and an input buffer. The I/O terminal receives a receive signal at a receive signal level that was transmitted from another integrated circuit at a transmitted signal level which is either a first or a second different signal level. The input buffer compares the receive signal to one or more reference signals to generate an input signal corresponding to the transmitted signal level based at least in part on the result of the comparison, even if the receive signal is received at a third signal level in between the first and the second signal level.

Abstract: Reconfigurable circuits and systems having a recovery module coupled to the reconfigurable circuit and configured to access the configuration memory to retrieve configuration data stored in the configuration memory. The recovery module analyzes the retrieved configuration data to determine whether the configuration data has been corrupted and, if so, restores the configuration data to their uncorrupted state. Methods of operating such reconfigurable circuits and systems are also described.

Abstract: A reconfigurable circuit having communication resources configured to facilitate selective packet-oriented communications among reconfigurable resources is described herein.

Abstract: A reconfigurable circuit having redundant reconfigurable clusters is described herein.

Abstract: A reconfigurable circuit having primary function blocks with runtime built-in self-test (BIST) circuitry, one or more redundant function blocks and runtime reconfiguration logic is described herein.

Abstract: An integrated circuit (IC) includes a number of function blocks (FB), of which at least one is re-configurable. Each of the FBs may be a reconfigurable function or a non-reconfigurable function or recursively expanded with additional “nested” function blocks. The IC further includes a number of input pins, a number of output pins, an adder, and a number of crossbar devices. The elements, at least at the IC level, are coupled in a manner such that all input signals are provided to the FBs through a first subset of the crossbar devices, all internal signals are routed from one FB to another FB through a second subset of crossbar devices, and all output signals are routed from the FBs to the output pins through a third subset of crossbar devices. To increase routability and speed each of the crossbar device output has a single fanout. Additionally, each of the crossbar devices may provide only one input to each other crossbar device.

Abstract: A reconfigurable circuit having redundant reconfigurable clusters is described herein.

Abstract: An integrated circuit (IC) includes a number of function blocks (FB), of which at least one is re-configurable. Each of the FBs may be a reconfigurable function or a non-reconfigurable function or recursively expanded with additional “nested” function blocks. The IC further includes a number of input pins, a number of output pins, an adder, and a number of crossbar devices. The elements, at least at the IC level, are coupled in a manner such that all input signals are provided to the FBs through a first subset of the crossbar devices, all internal signals are routed from one FB to another FB through a second subset of crossbar devices, and all output signals are routed from the FBs to the output pins through a third subset of crossbar devices. To increase routability and speed each of the crossbar device output has a single fanout. Additionally, each of the crossbar devices may provide only one input to each other crossbar device.

Abstract: Memory employing a plurality of five-transistor memory bit cells in a memory matrix and a power supply control circuit that is configured to provide a simultaneous full clear to all of the memory bit cells is described herein.

Abstract: Memory employing a plurality of five-transistor memory bit cells in a memory matrix and a power supply control circuit that is configured to provide a simultaneous full clear to all of the memory bit cells is described herein.

Abstract: An integrated circuit (IC) includes a number of function blocks (FB), of which at least one is re-configurable. Each of the FBs may be a reconfigurable function or a non-reconfigurable function or recursively expanded with additional “nested” function blocks. The IC further includes a number of input pins, a number of output pins, an adder, and a number of crossbar devices. The elements, at least at the IC level, are coupled in a manner such that all input signals are provided to the FBs through a first subset of the crossbar devices, all internal signals are routed from one FB to another FB through a second subset of crossbar devices, and all output signals are routed from the FBs to the output pins through a third subset of crossbar devices. To increase routability and speed each of the crossbar device output has a single fanout. Additionally, each of the crossbar devices may provide only one input to each other crossbar device.

Abstract: A reconfigurable circuit having primary function blocks with runtime built-in self-test (BIST) circuitry, one or more redundant function blocks and runtime reconfiguration logic is described herein.

Abstract: A reconfigurable circuit having primary function blocks with runtime built-in self-test (BIST) circuitry, one or more redundant function blocks and runtime reconfiguration logic is described herein.

Abstract: An integrated circuit (IC) includes a number of function blocks (FB), of which at least one is re-configurable. Each of the FBs may be a reconfigurable function or a non-reconfigurable function or recursively expanded with additional “nested” function blocks. The IC further includes a number of input pins, a number of output pins, an adder, and a number of crossbar devices. The elements, at least at the IC level, are coupled in a manner such that all input signals are provided to the FBs through a first subset of the crossbar devices, all internal signals are routed from one FB to another FB through a second subset of crossbar devices, and all output signals are routed from the FBs to the output pins through a third subset of crossbar devices. To increase routability and speed each of the crossbar device output has a single fanout. Additionally, each of the crossbar devices may provide only one input to each other crossbar device.

Abstract: Reconfigurable circuits with configuration data loaders are described herein. The configuration data loaders are adapted to enable on circuit finalization of configuration data provided in symbolic form, not fully resolved.