Abstract: A clock generator circuit includes a charge pump unit, a low-pass filter unit, a current-controlled clock generator and a voltage-to-current converter unit. The charge pump unit provides a pump current at an output terminal thereof. The low-pass filter unit is coupled to the output terminal of the charge pump unit, and develops a control voltage at an output terminal thereof based on the pump current. The voltage-to-current converter unit is coupled to the output terminal of the low-pass filter unit, the current-controlled clock generator and the charge pump unit, and provides a control current to the current-controlled clock generator. Each of the low-pass filter unit and the voltage-to-current converter unit includes a resistive element.

Abstract: A physical layer circuitry (PHY) includes: N signal pads, a four-signal physical medium attachment sublayer (PMA) and M shielding pads. The N signal pads include at least four signal pads. The four-signal PMA is coupled to the four signal pads. The M shielding pads include at least one first shielding pad that is coupled to the four-signal PMA. Additionally, the first shielding pin is located between a second signal pad of the four signal pads and a third signal pad of the four signal pads; and M and N are positive integers.

Abstract: A clock generation circuit arranged in a first system is disclosed. The clock generation circuit includes: a first dual-mode PLL, arranged for generating a first output clock in an integer-N mode or a fractional-N mode selectively, the first output clock being generated based on a first reference clock; and a second dual-mode PLL, arranged for generating a second output clock in an integer-N mode or a fractional-N mode selectively, the second output clock being generated based on the first output clock or a second reference clock selectively. Associated circuitries are also disclosed.

Abstract: A filter circuit includes an amplifier circuit, a resistor-capacitor (RC) network and a first voltage follower. The amplifier circuit has a first input terminal, a second input terminal and an output terminal. The amplifier circuit is configured to output a first output signal from the output terminal according to a first voltage signal at the first input terminal and a second voltage signal at the second input terminal. The RC network, coupled to the first input terminal, is configured to produce the first voltage signal at least in response to a first current signal applied to the first input terminal. The first voltage follower, coupled to the output terminal, is configured to receive the first output signal, and generate a first filtered signal in response to the first output signal.

Abstract: An integrated circuit includes a first multi-lane interface having a plurality of first lanes, a second multi-lane interface having a plurality of second lanes; a first layer of clock lane selection units arranged to select one or two of the first and second lanes and output signals on the one or two selected lanes; a second layer of clock lane selection units arranged to select the one or two selected lanes as one or two clock lane and output signals on the one or two selected clock lane; and a plurality of sampling units, each coupled to second layer of clock lane selection units, each arranged to sample one of the first and second lanes according to the signal on the selected clock lane.

Abstract: A circuit in a physical unit (PHY) is disclosed, the circuit comprising two trios and a combo wire therebetween, wherein each of said trios includes three wires, and wherein said combo wire is configurable as a signal, floating, or any dc voltage, furthermore, a Quad-IO block is designed for transmit data in two D-PHY lanes with the combo wire configured as a signal wire or a C-PHY trio with the combo wire configured as a shielding wire, such that the same Quad-IO block can be instantiated multiple times in a physical unit for meeting different bandwidth requirements as well as for placing pads along a same direction for preventing performance difference between D-PHY lanes or C-PHY trios.

Abstract: The present invention provides pad arrangements, termination circuits, clock/data recovery circuits, and deserialization architecture for a physical layer circuitry including a four-signal or six-signal physical medium attachment sublayer (PMA).

Abstract: A post-cursor compensation system includes a state detector that receives a signal on a data line to detect a predefined state, and accordingly generates a clear control signal; a synchronization detector that receives the signal on the data line and the clear control signal to detect at least one synchronization state, and accordingly generates a trigger signal; and a compensation generator that receives the trigger signal and accordingly generates a compensation signal.

Abstract: An integrated circuit with clock detection and selection function for use in a storage device includes: an embedded oscillator, a detection circuit and a selection circuit. The embedded oscillator is configured to generate an embedded clock signal. The detection circuit includes a sampling and counting circuit and a clock determination circuit. The detection circuit, and is configured to detect existence of a reference clock signal provided by a host based on sampling and counting operations that are performed according to a signal on a clock signal lane and the embedded clock signal. The selection circuit is coupled to the detection circuit and the embedded oscillator, and is configured to select one of the embedded clock signal and the signal on the clock signal lane according to the existence of the reference clock signal as an output clock signal, thereby to provide the output clock signal to the storage device.

Abstract: A SRAM module and a writing control method of the SRAM module are disclosed. The writing control method of the SRAM module is applied to a SRAM module that includes a plurality of memory cells and a bit line. The method includes: providing a first voltage as a supply voltage of the plurality of memory cells during a data retention time; decreasing a first voltage level corresponding to the data retention time of the memory cells to a second voltage level by discharging the memory cells; and performing a write process to the memory cells through the bit line. The discharge time from the first voltage level to the second voltage level is related to the number of the memory cells.

Abstract: A control device includes: a dummy memory cell group; a transistor having a first terminal, a grounded second terminal and a control terminal; an adjustor providing a resistance between the dummy memory cell group and the first terminal of the transistor; an inverter generating, based on a voltage at the first terminal of the transistor, a sense start signal that is associated with switching of a sense amplifier circuit of a semiconductor memory device from a disabled state to an enabled state; and a controller generating, based on the sense start signal, a control signal for controlling the transistor such that switching of the transistor from conduction into non-conduction is associated with the sense start signal.

Abstract: A SRAM module and a writing control method of the SRAM module are disclosed. The writing control method of the SRAM module is applied to a SRAM module that includes a plurality of memory cells and a bit line. The method includes: providing a first voltage as a supply voltage of the plurality of memory cells during a data retention time; decreasing a first voltage level corresponding to the data retention time of the memory cells to a second voltage level by discharging the memory cells; and performing a write process to the memory cells through the bit line. The discharge time from the first voltage level to the second voltage level is related to the number of the memory cells.

Abstract: A memory write tracking device is applied to a data write operation to at least a memory cell row. The memory write tracking device includes a dummy cell row, a variation sensor, a judging device and a word-line pulse generator. The dummy cell row includes a plurality of dummy memory cells for simulating the data write operation to the memory cell row. The variation sensor senses a set of circuit parameters for write ability of the memory cell row. The judging device determines a threshold number according to a change of the set of circuit parameters and sends an enabling signal when a threshold number of the dummy memory cells have been successfully written with the data. The word-line pulse generator determines a write cycle of the data write operation in response to the enabling signal. An associated memory write tracking method is also provided.

Abstract: The present invention discloses a random access memory and the memory access method thereof capable of avoiding read disturbance and increasing reading speed. An embodiment of the said random access memory comprises: a word line; a word line driving unit, coupled to the word line, operable to receive an access control signal to generate a word line enablement voltage; a voltage adjusting unit including a switch and a capacitor in which the switch is coupled to the word line and operable to receive a control signal to determine a conduction state of the switch itself and the capacitor is coupled to the switch and operable to adjust a voltage level of the word line enablement voltage according to the conduction state; and a memory unit, coupled to the word line, operable to be enabled according to the word line enablement voltage.

Abstract: A voltage generating circuit includes: (1) a driving unit having an input terminal and an output terminal, wherein the input terminal is configured to receive an input signal, wherein when the input signal is at a first logic level, power is configured to be charged from a first voltage terminal to the output terminal, and when the input signal is at a second logic level, power is configured to be discharged from the output terminal to a second voltage terminal; (2) a first switch configured to couple the second voltage terminal to a capacitance-compensating terminal based on the input signal; (3) a compensating capacitor configured to be coupled between the capacitance-compensating terminal and a third voltage terminal; and (4) a second switch configured to couple the capacitance-compensating terminal to a fourth voltage terminal based on the input signal.

Abstract: A phase detector includes a plurality of sampling circuits, a logic circuit, a plurality of demultiplexers and a decision circuit, wherein the plurality of sampling circuits use a plurality of clock signals with different phases to sample a data signal respectively to generate a plurality of sampling results; the logic circuit generate N phase-leading signals and N phase-lagging signals according the plurality of sampling results; the plurality of demultiplexers perform demultiplex operations to the N phase-leading signals and the N phase-lagging signals respectively to generate M phase-leading output signals and M phase-lagging output signals respectively; and the decision circuit generates a final phase-leading signal and a final phase-lagging signal according the M phase-leading output signals and the M phase-lagging output signals.

Abstract: A pulse width modulation device for use in an N-ports random access memory having a plurality of word line sets, wherein a specified word line set comprises N port word lines. The pulse width modulation device comprises a status detecting device and a clock signal generator. The status detecting device is coupled to the N port word lines having a first and a second port word line, and outputs a first control signal when both the voltage values of the first and second port word lines are within a first level range. The clock signal generator is coupled to the status detecting device and the specified word line set, and generates and outputs a first clock signal to the specified word line set, wherein a duration of the first clock signal kept within the first level range is variable in response to the first control signal.

Abstract: The invention provides a method for transmitting a signal to an external electronic device. The method includes obtaining a compensation value by which an equalizer compensates a signal transmitted from the external electronic device, comparing the compensation value with a set of reference values so as to obtain one or more parameters, and adjusting an output signal transmitted from a transmit unit to the external electronic device based on the one or more parameters.

Abstract: A multi-port SRAM module includes a cell array comprising a plurality of cells, each having a first port and a second port; a first word line which is coupled to a plurality of cells of a target row to open and close the first port; a second word line which is coupled to the cells of the target row to open and close the second port; and a switch, which is coupled to the first word line and the second word line and couples the second word line to a reference voltage level according to a voltage level of the first word line.

Abstract: A static random access memory (SRAM) includes a voltage generator coupled to receive a positive power supply voltage, and to controllably generate a first power supply voltage, which is with a reduced level and is higher than a retention voltage during a specific period. A first inverter and a second inverter each is connected between the first power supply voltage and a second power supply voltage. The first inverter and the second inverter are cross-coupled, and the output nodes of the first inverter and the second inverter act as a bit node pair.