Abstract: Semiconductor structures with reduced parasitic capacitance between interconnects and ground, for example, are described. An example method for making a semiconductor structure includes forming a trench in an interconnect area of a substrate between first and second device areas in the semiconductor structure, forming a low dielectric constant material region in the trench, forming a III-nitride material layer over the substrate and over the low dielectric constant material region in the trench, forming a first device in the III-nitride material layer in the first device area, forming a second device in the III-nitride material layer in the second device area, and forming an interconnect over the low dielectric constant material region, the interconnect comprising a continuous conductive metal interconnect from the first device area, over the low dielectric constant material region, and to the second device area.

Abstract: Extrinsic structures formed outside the active regions of active devices can influence aging characteristics and performance of the active devices. An example integrated device including such an extrinsic structure includes an active region of a semiconductor device in a plurality of layers of semiconductor materials over a substrate, an isolation region in at least one of the layers of semiconductor materials, the isolation region extending around the semiconductor device in an area outside of the active region, an insulating layer over at least a portion of the active region and over at least a portion of the isolation region, a via in the isolation region and outside the active region, the via extending through the insulating layer and down to a conduction layer among the layers of semiconductor materials in the isolation region, and an interconnect within the via and directly on the conduction layer in the isolation region.

Abstract: Athermal arrayed waveguide grating structure that may operate as an optical filter including an input Silicon (Si) slab waveguide, an output Si slab waveguide, the input Si slab waveguide and the output Si slab waveguide optically connected by an arrayed group of Silicon Nitride (SiN) grating waveguides. Temperature insensitivity of the structure is achieved by locating output waveguide(s) of the Si output slab waveguide at/within a 10-degree angle offset from the center line of the output Si slab waveguide.

Abstract: A driver electronic circuit for a pulse amplitude modulation transmitter includes a plurality of transmission lanes. Each transmission lane is configured to independently generate a current output corresponding to data input into each transmission lanes. The driver electronic circuit also includes a summing node configured to sum the output currents from the plurality of transmission lanes. The driver electronic circuit further includes one feedback loop circuit coupled to the plurality of transmission lanes configured to control the currents of each said current outputs. The driver electronic circuit may be configured to drive a vertical-cavity surface-emitting laser for optical communication.

Abstract: A transistor device includes a metal submount; a transistor die arranged on said metal submount; a first integrated passive device (IPD) component that includes a first substrate arranged on said metal submount; and a second integrated passive device (IPD) component that includes a second substrate arranged on the metal submount. Additionally, the first substrate is a different material from the second substrate.

Abstract: A transistor includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other. The first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. A resistor is disposed in the gap region.

Abstract: A radio frequency (RF) package includes a support having a semiconductor die attach region; a frame that includes an electrically insulative member having a lower side attached to the support and an upper side opposite the support; the frame includes an opening at least partially registered with said semiconductor die attach region; and the frame includes an upper metallization at the upper side of the electrically insulative member and a lower metallization The frame includes first electrically conductive edge connection connecting the first metallization to the first lower metallization.

Abstract: Disclosed are various embodiments for a multi-tip laser coupler with improved alignment guidance. A photonic integrated circuit (PIC) includes an input interface, an output interface, and a waveguide array. The waveguide array includes a first waveguide, a second waveguide, and a third waveguide. The first waveguide and the third waveguide are coupled to the input interface and are not coupled to the output interface. The second waveguide is coupled to the input interface and the output interface. Further, the second waveguide is positioned parallel to and between the first waveguide and a third waveguide. The second waveguide includes a tapered body such that an output end of the second waveguide coupled to the output interface is wider than an input end of the second waveguide coupled to the input interface.

Abstract: An angular deviation optical tracking and detector device for use in optical systems such as a FSO communication systems—among others. The angular deviation optical tracking and detector device includes position sensor elements that are configured to detect any misalignment of incoming/received light and an optical tunnel structure coupled with a detector array to determine the angular deviation. The optical tracking and detector device includes a position sensor having an optical aperture configured to allow a portion of incoming light to pass through the position sensor; a plurality of position receivers positioned adjacent to the optical aperture, the plurality of position receivers configured to sense portions of the incoming light; and an optical detector array configured to detect portions of the incoming light that passes through the position sensor aperture and optical tunnel. Angular deviation may be determined from diode array readout of illuminated individual diodes.

Abstract: An acoustic wave resonator has a first conductive layer, piezoelectrical material formed over the first conductive layer, and second conductive layer formed over the piezoelectric material. An alignment of the first conductive layer, piezoelectric material and second conductive area defines an active region of the resonator and the active region includes a core area and a plurality of fractals extending from or recessed into the core area. The fractals maximize a perimeter-to-area ratio of the active region of the resonator. The fractals increase electromechanical coupling and a quality factor of the resonator. The fractals can have a star shape, rounded shape, asymmetric shape, or other shape that optimizes the perimeter-to-area ratio of the active region to maximize performance of the resonator. A frame can be disposed over or within the piezoelectric material. The frame is raised above the second conductive layer or recessed below the second conductive layer.

Abstract: An RF transistor amplifier circuit comprises a Group III nitride based RF transistor amplifier having a gate terminal, a Group III nitride based self-bias circuit that includes a first Group III nitride based depletion mode high electron mobility transistor, the Group III nitride based self-bias circuit configured to generate a bias voltage, and a Group III nitride based depletion mode differential amplifier that is configured to generate an inverted bias voltage from the bias voltage and to apply the inverted bias voltage to the gate terminal of the Group III nitride based RF transistor amplifier. The Group III nitride based RF transistor amplifier, the Group III nitride based self-bias circuit and the Group III nitride based depletion mode differential amplifier are all implemented in a single die.

Abstract: A number of Monolithic Microwave Integrated Circuit (MMIC) devices including combinations of PIN and Schottky diodes, with integrated passive electrical components fabricated and electrically connected among them, are described herein, along with new process techniques for forming the MMIC devices. In one example, a monolithic semiconductor includes a substrate, a plurality of layers of semiconductor materials over the substrate, Schottky and Ohmic contacts on a first subset of the plurality of layers for a Schottky diode, and PIN diode Ohmic contacts on a second subset of the plurality of layers for a PIN diode. The device can also include an etch stop layer between the first subset of the plurality of layers and the second subset of the plurality of layers. The etch stop layer facilitates selective etching and isolation of the Schottky diode from the PIN diode by consecutive etchings.

Abstract: A level shifter, configured to shift an input voltage swing from a first voltage range to a second voltage range, comprising a first stage and a switching stage, with circuitry configured in isolation wells. The first stage includes a first stage input receiving an input signal that swings between a first voltage value and a second voltage, a buffer configured to shift the input signal to vary between a third value and a fourth value, and a first stage output configured to present a first stage output signal. The switching stage comprises switching stage inputs, configured to receive the first stage output signal, switch drivers, and switching devices configured to, responsive to the driver output, generate a switching stage output signal that is a shifted version of the input signal. The switching stage output signal ranges between a fifth voltage value and a sixth voltage value.

Abstract: Semiconductor devices are provided that include a Group III nitride-based semiconductor layer structure. A first metal layer is formed on an upper surface of the semiconductor layer structure, a first dielectric layer is formed on an upper surface of the first metal layer, and a second metal layer is formed on an upper surface of the first dielectric layer. The first metal layer, the first dielectric layer and the second metal layer form a first capacitor. A second dielectric layer is formed on an upper surface of the second metal layer, a third dielectric layer is formed on an upper surface of the second dielectric layer, and a third metal layer is formed on upper surfaces of the second and third dielectric layers. The second metal layer, the second dielectric layer and the third metal layer form a second capacitor that is stacked on the first capacitor.

Abstract: A phase interpolator with a DAC outputting a first and second value responsive to a control code. A first current mirror generates a first current proportional to the first value. A second current mirror generates a second current proportional to the second value. A first FET pair comprising a first and second FET such that the source terminals of the first FET and the second FET are electrically connected and connect to the first current mirror. A second FET pair comprising a third and fourth FET such that the source terminals of the third FET and the fourth FET are electrically connected and connect to the second current mirror. A first terminal outputs a phase adjusted clock signal as compared to the clock signal, from the first FET and the third FET. A second terminal outputs an inverted phase adjusted clock signal, from the second FET and the fourth FET.

Abstract: A semiconductor optical device includes a first facet bounding a first end of the semiconductor optical device. The semiconductor optical device further includes a waveguide having a first end proximate the first facet, the first end of the waveguide being tapered towards the first facet. The first facet has a curvature to increase modal reflectivity at a first interface at which the first end of the waveguide meets the first facet.

Abstract: A coupling system in an integrated circuit to block DC components from an amplifier without large costly external coupling capacitors. An input receives an input signal which has a DC component. A first impedance element receives the input signal and blocks the DC component while a second impedance element connects between the output of the first impedance matching element and a ground node. The second impedance element and the first impedance element form a voltage divider network. The first and second impedance element are integrated elements. The amplifier receives the input signal after the DC component is blocked. The first impedance element and the second impedance element may comprise a resistor in series with a capacitor. In a differential pair configuration, an impedance matching element interconnects between a first path and a second path to impedance match the amplifier to a data source.

Abstract: A metal-insulator-metal (MIM) capacitor component that includes a substrate, where the metal-insulator-metal (MIM) capacitor component is configured to form a first capacitor with a top metal and a first bottom metal having a dielectric layer therebetween; and where the metal-insulator-metal (MIM) capacitor component is configured to form a second capacitor with the top metal and a second bottom metal having the dielectric layer therebetween. Additionally, the top metal, the dielectric layer, the first bottom metal, and the second bottom metal are arranged on the substrate.

Abstract: A transistor amplifier includes a semiconductor layer structure comprising first and second major surfaces and a plurality of unit cell transistors on the first major surface that are electrically connected in parallel, each unit cell transistor comprising a gate finger coupled to a gate manifold, a drain finger coupled to a drain manifold, and a source finger. The semiconductor layer structure is free of a via to the source fingers on the second major surface.

Abstract: A semiconductor device comprises a lead, a board, and an electrically conductive layer on the board. The lead comprises a longitudinal axis and is soldered to the electrically conductive layer. The semiconductor device further comprises a first solder dam edge and a second solder dam edge, each positioned on the lead not more than 10 mils apart from each other along the longitudinal axis.