Abstract: A three-dimensional flash memory device may be a AND flash memory device. The three-dimensional flash memory device includes: a substrate, a gate stack structure, a plurality of slit structures, a plurality of memory arrays, and a plurality of conductive pillars. The gate stack structure is located above the substrate. The plurality of slit structures extend through the gate stack structure and divide the gate stack structure into a plurality of blocks. The plurality of memory arrays are disposed in the gate stack structure of the plurality of blocks. The plurality of conductive pillars extends through the gate stack structure in the plurality of blocks, and disposed between the plurality of memory arrays and between the plurality of slit structures.

Abstract: A memory device and an in-memory search method thereof are provided. The memory device includes a first memory cell block, a second memory cell block, at least one search memory cell pair, and a sense amplifier. The search memory cell pair includes a first search memory cell and a second search memory cell. The first search memory cell and the second search memory cell are respectively disposed in the first memory cell block and the second memory cell block. The first search memory cell and the second search memory cell respectively receive a first search voltage and a second search voltage. The first search voltage and the second search voltage are generated according to searched data. The sense amplifier generates a search result according to signals on a first bit line and a second bit line.

Abstract: An in-memory computation device and computation method are provided. The in-memory computation method includes: providing a memory cell block of a memory cell array to store a plurality of weight values, and providing a plurality of memory cells on the memory cell block to store a plurality of corresponding bits of each of the weight values; respectively transmitting a plurality of input signals to the plurality of bit lines through an input buffer; providing the plurality of memory cells to perform a multiplication operation of the plurality of input signals and the plurality of weight values to generate a plurality of first operation results respectively corresponding to a plurality of bit orders; and performing an addition operation on the plurality of first operation results to generate a second operation result according to the plurality of bit orders by a sense amplifier.

Abstract: A method of programming a memory includes performing a plurality of programming shots is provided. Each programming shot includes a pre-charge stage and a programming stage and includes the following steps. Applying a common source line voltage to a common source line or applying a bit line voltage to a bit line in the pre-charge stage, wherein the common source line voltage or the bit line voltage is applied by using incremental-step-pulse programming (ISSP) in the plurality of pre-charge stages. Applying a programming voltage to a selected word line in the programming stage, wherein the programming voltage is applied by using ISSP in the plurality of programming stages.

Abstract: An operation method of an artificial neural network is provided. The operation method includes: dividing input information into a plurality of sub-input information, and expanding kernel information to generate expanded kernel information; performing a Fast Fourier Transform (FFT) on the sub-input information and the expanded kernel information to respectively generate a plurality of frequency domain sub-input information and frequency domain expanded kernel information; respectively performing a multiplying operation on the frequency domain expanded kernel information and the frequency domain sub-input information to respectively generate a plurality of sub-feature maps; and performing an inverse FFT on the sub-feature maps to provide a plurality of converted sub-feature maps for executing a feature extraction operation of the artificial neural network.

Abstract: A 3D flash memory module chip includes a memory chip and a control chip. The memory chip includes a plurality of tiles and a plurality of heaters. The tiles each include a plurality of 3D flash memory structures. The heaters are disposed around the 3D flash memory structures of each of the tiles. The control chip is bonded with the memory chip to drive at least one of the heaters.

Abstract: Systems, methods, circuits, and apparatus for managing multi-block operations in memory devices are provided. In one aspect, a memory device includes a memory cell array including at least two blocks, a bit line coupled to a string of memory cells in each of the at least two blocks respectively, a common source line (CSL) coupled to strings coupled to the bit line in the at least two blocks, and a circuitry configured to perform a multi-block operation in the memory cell array by at least one of: forming a first current path from the bit line through the strings to the CSL coupled to a ground to discharge a capacitor associated with the bit line that is pre-charged, or forming a second current path from the CSL coupled to a supply voltage through the strings to the bit line to charge the capacitor that is pre-discharged.

Abstract: Systems, devices, methods, and circuits for managing data security in storage devices. In one aspect, a storage device includes at least one memory device and a controller coupled to the at least one memory device. The controller is configured to: encrypt first data with a first type of cryptographic algorithm and encrypt second data with a second type of cryptographic algorithm. The first data is associated with a first security level, and the second data is associated with a second security level that is higher than the first security level. The second type of cryptographic algorithm has a greater encryption strength than the first type of cryptographic algorithm.

Abstract: A 3D memory including a plurality of tiles, a bit line transistor structure, a first upper conductive layer, and a second upper conductive layer. The bit line transistor structure is disposed between a first sub-tile and a second sub-tile in the plurality of tiles. The first upper conductive layer includes a plurality of local bit lines, a plurality of local source lines and a conductive pattern. The plurality of local bit lines include a first group and a second group of local bit lines separated from each other, wherein two adjacent local bit lines are disposed between adjacent two local source lines. The second upper conductive layer includes a global bit line. The global bit line is electrically connected to the local bit lines through the conductive pattern. The 3D memory could be a 3D AND flash memory with high capacity and high performance.

Abstract: Methods, devices, apparatus, and systems for managing phase change materials for memory devices are provided. In one aspect, an integrated circuit (e.g., a memory element) includes: a first electrode, a second electrode, and a body of a phase change material coupled between the first electrode and the second electrode. The phase change material includes SixSbyTez, where x, y, z represent respective atomic ratios for compositions Si, Sb, Te. A bulk stoichiometry of the body of the phase change material includes a Si atomic concentration within a range from about 7% to about 12%.

Abstract: An electronic circuit includes: a data input port, a timing adjustment circuit configured to receive data from the data input port, first and second logic circuits, a multiplexer, and a data output port. The timing adjustment circuit includes two paths configured to impose first and second delays to generate first and second delayed data. The first and second logic circuits are configured to respectively receive the first and second delayed data and generate first and second logic outputs. The first logic output expands a pulse width corresponding to a first logic value. The second logic output expands a pulse width corresponding to a second logic value. The multiplexer is configured to select, based on an equalization feedback, at least one of the first logic output or the second logic output, to provide the multiplexer output. The data output port is configured to output equalized data based on the multiplexer output.

Abstract: A memory device and a programming method thereof are provided. The memory device has multiple word lines and a dummy word line set. A word line is selected from the word lines and is applied with a program voltage, and unselected word lines and the dummy word line set are applied with a pass voltage. After programming the selected word line, a program verification is performed on the selected word line. When the selected word line passes the program verification, a high bound and/or low bound check for the threshold voltage distribution of at least one of the dummy word lines is performed. When at least one of the dummy word lines fails in the high bound and/or low bound check, the status of the selected word line is shown as fail or a flag is set thereto.

Abstract: An in-memory computation device includes multiple computation blocks, a first reference weight block, and an output result generator. The computation blocks have multiple weighting values, receive multiple input signals respectively, and generate multiple computation results. Each of the computation blocks generates each of the computation results according to each of the corresponding input signals and corresponding weighting values. The first reference weight block provides a first reference resistance according to multiple reference weighting values and generates a first reference signal according to the first reference resistance and a read voltage. The output result generator generates multiple output computation results according to the first reference signal and the computation results.

Abstract: Systems, methods, circuits, and devices for managing data transfers in semiconductor devices are provided. In one aspect, a method includes: selecting a first interface to receive higher-speed-type data at a first clock frequency; transferring the higher-speed-type data with a first speed along a first data path from the first interface through a first logic circuit to a driving circuit; outputting the higher-speed-type data by the driving circuit; selecting a second interface to receive lower-speed-type data at a second clock frequency that is same as the first clock frequency; transferring the lower-speed-type data with a second speed along a second data path from the second interface through a second logic circuit to the driving circuit, the first speed being higher than the second speed; and outputting the lower-speed-type data by the driving circuit.

Abstract: A memory device includes a memory cell array including memory cells; a page buffer circuit including a plurality of page buffers coupled to the memory cell array, each page buffer including a plurality of latches and an internal data line (IDL) arranged to couple to the plurality of latches; and a cache circuit including a plurality of caches. The IDLs of the plurality of page buffers are configured to be conductively connected together to form a data bus (DBUS) that conductively connects the page buffer circuit to the cache circuit for data transfer.

Abstract: A memory device includes a gate stack structure, a channel pillar, a plurality of conductive pillars, and a charge storage structure. The gate stack structure is located over a dielectric substrate, and includes a plurality of gate layers and a plurality of insulating layers stacked alternately with each other. The channel pillar extends through the gate stack structure. Each of the conductive pillars includes a body portion and an extension portion. The body portion extends through the gate stack structure and is electrically connected to the channel pillar. The extension portion is below and is electrically isolated from the channel pillar. The charge storage structure is between the channel pillar and the plurality of gate layers.

Abstract: A duty cycle correction method and a duty cycle correction system, adapted for correcting a duty cycle of a clock signal by using a duty cycle corrector (DCC) in a high-capacity and high-performance semiconductor product such as a 3D NAND flash, are provided. In the method, training is performed on the DCC to correct the clock signal, and a training result is recorded after the training is finished; and the DCC is updated by the recorded training result before a next toggle of the clock signal.

Abstract: A memory device includes: an interconnect structure, a staircase structure, a dielectric layer and a stop structure. The interconnect structure is located above a substrate. The staircase structure is located above the interconnect structure. The dielectric layer is located above the interconnect structure and covers the staircase structure. The stop structure is located between the interconnect structure and the staircase structure, and between the interconnect structure and the dielectric layer, and the stop structure has an opening exposing the interconnect structure. The first contact extends through the dielectric layer and the opening, and is connected to the interconnect of the interconnect structure. The middle width of the opening is not equal to the top width of the opening, or the middle width of the opening is not equal to the bottom width of the opening. The memory device may be 3D NAND flash memory with high capacity and high performance.

Abstract: A memory device includes a substrate, a bonding structure and bit lines. The substrate includes adjacent first and second regions. The bonding structure is over the substrate and includes a bonding dielectric layer and first and second bonding pads. The bonding dielectric layer is over the substrate in the first and the second regions. The first and second bonding pads are respectively embedded in the bonding dielectric layer over the substrate in the first and second regions. The bit lines are over the bonding structure and extend from the first region to the second region. A density of the first bonding pads in the first region is greater than a density of the second bonding pads in the second region. The memory device may be 3D NAND flash memory with high capacity and high performance.

Abstract: A memory structure including a memory array is provided. The memory array is a block including six sub-blocks. The memory array includes string select line portions and ground select line portions. The string select line portions are arranged along a first direction. Each of the string select line portions is located in the corresponding sub-block. The ground select line portions are arranged along the first direction. Each of the ground select line portions is shared by only two corresponding sub-blocks. The memory structure may be a 3D NAND flash memory with high capacity and high performance.