Abstract: A phase change memory cell. The phase change memory cell includes a substrate and a phase change material. The phase change material is deposited on the substrate for performing a phase change function in the phase change memory cell. The phase change material is an alloy having a mass density change of less than three percent during a transition between an amorphous phase and a crystalline phase.

Abstract: A phase change memory cell. The phase change memory cell includes a substrate and a phase change material. The phase change material is deposited on the substrate for performing a phase change function in the phase change memory cell. The phase change material is an alloy having a mass density change of less than three percent during a transition between an amorphous phase and a crystalline phase.

Abstract: A phase change memory cell. The phase change memory cell includes a substrate and a phase change material. The phase change material is deposited on the substrate for performing a phase change function in the phase change memory cell. The phase change material is an alloy having a mass density change of less than three percent during a transition between an amorphous phase and a crystalline phase.

Abstract: A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts.

Abstract: A raised-Vs Channel Initialed Secondary Electron Injection is disclosed to program a charge-trapping nonvolatile memory cell. The source of the charge-trapping nonvolatile memory cell is applied with a positive source voltage, and the drain of the charge-trapping nonvolatile memory cell is applied with a positive drain voltage, wherein the positive drain voltage is greater than the positive source voltage. The substrate of the charge-trapping nonvolatile memory cell is grounded. A positive gate voltage is applied to the polysilicon gate of the charge-trapping nonvolatile memory cell.

Abstract: For non-volatile memory devices, such as flash EPROM integrated circuits, which have memory cells and reference cells, and sense circuitry responsive to addressed memory cells and the reference cells, and in which a read potential is supplied to the gate of the selected memory cells and a reference potential is supplied to the gate of a reference memory cell during a read mode, the state of the programmable memory cells is verified by (1) supplying a first verify potential to the gate of an address programmable memory cell; and (2) supplying a second verify potential to the gate of the reference cell which is different from the first verify potential. Because cell current is a very strong function of the gate voltage, applying different gate voltages to the memory and reference cells is equivalent to adjusting the sense ratio.