Abstract: The templatized memory pattern generator includes a test processor, a simple memory pattern generator, a channel timing & formatter, and a pin electronic. The simple memory pattern generator includes an X address generator, a Y address generator, a D data generator, a SMPG and channel mapping. An input terminal of the channel timing & formatter is connected to the SMPG and channel mapping; and parallel data calculated by the simple memory pattern generator based on an SMPG resource mapping table provided by an upper computer is mapped to pins of a device under test one by one. The present disclosure can effectively reduce a quantity of test vectors in an image file. Meanwhile, after modulation, the scheme can improve the reusability of a test program and reduce the development period of the test scheme.