Abstract: An integratable phase locked loop (IPLL) comprising sampled data filter means adapted to receive a first reference signal, the filter means sampling the first reference signal (Ref In) to provide a second reference signal (Control Volts Out), and voltage or current controlled oscillator (VCO) means adapted to receive said second reference signal, the second signal serving to regulate the frequency of oscillation of the oscillator, the oscillator providing as an output a digital signal which is fed back to the filter means to provide a clock signal (CLK) for said sampling.

Abstract: A regulator is provided for receiving electrical power from an external alternating magnetic field and developing a regulated output voltage. The regulator is operatively coupled to a resonant inductive circuit for obtaining input power. It includes a circuit for regulating output power by shunting input power and providing separate current paths for shunt current and output current. The circuit includes a rectifier in the output current path. The regulator is integrated on a single VLSI chip.