Abstract: The preset invention discloses an improved method for fabricating a MOSFET transistor on a substrate to improve the device ruggedness. The fabrication method includes the steps of: (a) forming an epi-layer of a first conductivity type as a drain region on the substrate and then growing an gate oxide layer over the epi-layer; (b) depositing an overlaying polysilicon layer thereon and applying a polysilicon mask for etching the polysilicon layer to define a plurality of polysilicon gates; (c) removing the polysilicon mask and then carrying out a body implant of a second conductivity type followed by performing a body diffusion for forming a plurality of body regions; (d) performing a high-energy body-conductivity-type-dopant implant, eg., boron implant, to form a plurality of shallow low-concentration regions of source-conductivity-type, e.g., n-regions, under each of e gates.

Abstract: This invention discloses a semiconductor substrate supports a semiconductor power device. The semiconductor substrate includes a plurality of polysilicon segments disposed over a gate oxide layer including two outermost segments and inner segments wherein each of the inner segments functioning as a gate and the two outermost segments functioning as a field pate and an equal potential ring separated by an oxide-plug gap having an aspect ratio greater or equal to 0.5. Each of the inner segments functioning as a gate having a side wall spacer surrounding edges of the inner segments, and the oxide plug gap being filled with an oxide plug for separating the field plate from the equal potential ring. A plurality of power transistor cells disposed in the substrate for each of the gates covered by an overlying insulation layer having a plurality of contact openings defined therein.

Abstract: This invention discloses a DMOS power device supported on a substrate. The DOS power device includes a drain of a first conductivity type disposed at a bottom surface of the substrate. The DMOS power device further includes a gate disposed in a trench opened from a top surface of the substrate, the gate having a polysilicon layer filling the trenches padded by a double gate-oxide structure. The double gate-oxide structure includes a thick-oxide-layer covering walls of the trench below an upper portion of the trench and a thin-gate-oxide covering walls of the upper portion of the trench thus defining a champagne-glass shaped gate in the trench. The DMOS power device further includes a source region of the first conductivity type disposed in the substrate surrounding a top portion of the trench. The DMOS power device further includes a body region of a second conductivity type disposed in the substrate surrounding the trench and encompassing the source region.

Abstract: This invention discloses a vertical DMOS transistor cell formed in a semiconductor substrate of a first conductivity type with a top surface and a bottom surface. The vertical DMOS transistor cell includes a trenched gate comprising polysilicon filling a trench opened from the top surface disposed substantially in a middle portion of the cell. The DMOS transistor cell further includes a source region of the first conductivity type surrounding the trenched gate near the top surface of the substrate. The DMOS transistor cell further includes a body region of a second conductivity type encompassing the source region. The body region surrounding the trenched gate and extends vertically to about one-half to two-third of the depth of the trenched gate. The body region further includes a body-dopant redistribution-compensation region under the source region near the trenched gate having a delta-increment body dopant concentration distribution higher than remaining portions of the body region.

Abstract: A MOSFET (Metal Oxide Semiconductor Field Effect Transistors) structure is fabricated by first forming a plurality of trenches in a semiconductor substrate which includes a major surface. The trenches are then lined with insulating material and thereafter filled with conductive material. The process of filling the conductive material in the trenches normally involves an over-etching step for preventing any residual material remaining on the major surface. The over-etching of the conductive material in the trenches alters the evenness of the major surface and presents a problem for the later angular ion implantation of the source layer. As a consequence, the source layer formed includes asymmetrical source segments which generates nonuniform threshold voltage and punch-through tolerance in the MOSFET structure. The inventive method provides a spacer layer to compensate for the unevenness of the major surface.

Abstract: The present invention discloses a method for fabricating a MOSFET device supported on a substrate.

Abstract: This invention discloses a vertical DMOS power device formed in a semiconductor substrate with a top surface and a bottom surface. The power device includes a core cell area and a gate runner area. The power device includes a plurality of vertical DMOS transistor cells disposed in the core cell area wherein each transistor cell includes a drain of a first conductivity type disposed at the bottom surface of the substrate. Each of the DMOS transistor cells further includes a trench surrounding the cell having a polysilicon disposed in the trench defining a gate for the transistor cell. Each of the transistor cells further includes a source region of the first conductivity type disposed in the substrate near the gate. Each of the transistor cells further includes a body region of a second conductivity type disposed in the substrate between the gate wherein the body region defining a vertical current channel along the trench between the source and the drain.

Abstract: A MOSFET (Metal Oxide Semiconductor Field Effect Transistors) cell array formed on a semiconductor substrate includes a major surface formed with a plurality of MOSFET cells. Each semiconductor cell in the cell array is geometrically configured with a base portion and a plurality of protruding portions extending from the base portion. The base and protruding portions define a closed cell boundary enclosing each semiconductor cell. The closed cell boundary of each semiconductor cell is disposed on the major surface proximal to and in geometrical accord with the corresponding cell boundaries of other adjacent semiconductor cells in the cell array. As arranged, the cell boundary and thus the channel width of each cell is extended without any concomitant reduction in cell area.

Abstract: A trenched gate MOSFET (metal oxide semiconductor field effect transistor) structure is fabricated via a novel process which includes the step of using a common mask serving the dual role as a mask for the body layer formation and as a mask for trench etching. The common mask defines an patterned oxide layer which includes a plurality of openings at a predetermined distance away from the scribe line of the MOSFET structure. During fabrication, material of the body layer is implanted through the openings of the patterned oxide layer. Thereafter, the implanted material is side-diffused and merged together under a drive-in cycle as one continuous body layer. Using the same patterned oxide layer as a shield, trenches are anisotropically etched in the substrate. The MOSFET structure as formed requires no separate mask for delineating the active body region away from the scribe line, resulting reduction of fabrication steps. The consequential benefits are lower manufacturing costs and higher production yields.

Abstract: A power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device formed on a semiconductor substrate having a body region of a first conductivity type diffused in a semiconductor substrate with an epitaxial layer of a second conductivity type. There is also a source region of a second conductivity type formed in the body region. A portion of the body region adjacent to the source region is compensated by ion implanting a material of the second conductivity type in the portion of the body region such that the impurity concentration of the body region at the portion is reduced. As a consequence, with reduced impurity charge in the body region adjacent to the source, the threshold voltage of the MOSFET device is lowered but at no comprise in punch-through tolerance because the reduction in charge is remote from the origin of the depletion layer which is located at the boundary between the body region and the epitaxial layer.

Abstract: A MOSFET device formed in a semiconductor chip with a top surface and a bottom surface. The MOSFET device includes a drain region doped with impurities of a first conductivity type, formed near the bottom surface. The MOSFET device further includes a plurality of vertical cells wherein each of the vertical cell includes a vertical pn-junction zone region includes a lower-outer body region, doped with impurities of a second conductivity type, formed on top of the drain region. The pn-junction region further includes a source region, doped with impurities of the first conductivity type, formed on top of the lower-outer body region, the lower-outer body region surrounding the source region and extending to the top surface thus defining a cell area for the cell. The vertical cell further includes a source contact formed on the top surface contacting the source region. The MOSFET further includes a plurality of gates.