Abstract: Systems and methods for realizing reference currents to improve reliability of sensing operations of segmented semiconductor memory arrays have been achieved. Preferred embodiments of the invention comprise MRAM arrays but the invention could be applied to any other memories requiring access on small, segmented arrays. All embodiments of the invention comprise a folded bit lines scheme, either in adjacent bit lines or in segment-to-segment folded bit lines. In two embodiments alternate strapping of Poly-Si Word Lines in every second segment is achieved by metal layer of Read Word Line and Write Select Line. An embodiment has stored 1 and 0 cells on both sides of a selected segment to be read.

Abstract: A STT-RAM MTJ is disclosed with a MgO tunnel barrier formed by natural oxidation process. A Co10Fe70B20/NCC/Co10Fe70B20, Co10Fe70B20/NCC/Co10Fe70B20/NCC, or Co10Fe70B20/NCC/Co10Fe70B20/NCC/Co10Fe70B20 free layer configuration where NCC is a nanocurrent channel layer made of Fe(20%)-SiO2 is used to minimize Jc0 while enabling higher thermal stability, write voltage, read voltage, Ho, and Hc values that satisfy 64 Mb design requirements. The NCC layer is about 10 Angstroms thick to match the minimum Fe(Si) grain diameter size. The MTJ is annealed with a temperature of about 330° C. to maintain a high magnetoresistive ratio while maximizing Hk?(interfacial) for the free layer thereby reducing Heff and lowering the switching current. The Co10Fe70B20 layers are sputter deposited with a low pressure process with a power of about 15 Watts and an Ar flow rate of 40 standard cubic centimeters per minute to lower Heff for the free layer.

Abstract: A STT-RAM MTJ that minimizes spin-transfer magnetization switching current (Jc) is disclosed. The MTJ has a MgO tunnel barrier layer formed with a natural oxidation process to achieve a low RA (10 ohm-um2) and a Fe or Fe/CoFeB/Fe free layer which provides a lower intrinsic damping constant than a CoFeB free layer. A Fe, FeB, or Fe/CoFeB/Fe free layer when formed with a MgO tunnel barrier (radical oxidation process) and a CoFeB AP1 pinned layer in a MRAM MTJ stack annealed at 360° C. provides a high dR/R (TMR)>100% and a substantial improvement in read margin with a TMR/Rp_cov=20. High speed measurement of 100 nm×200 nm oval STT-RAM MTJs has shown a Jc0 for switching a Fe free layer is one half that for switching an amorphous Co40Fe40B20 free layer. A Fe/CoFeB/Fe free layer configuration allows the Hc value to be increased for STT-RAM applications.

Abstract: A MTJ that minimizes spin-transfer magnetization switching current (Jc) in a Spin-RAM to <1×106 A/cm2 is disclosed. The MTJ has a Co60Fe20B20/MgO/Co60Fe20B20 configuration where the CoFeB AP1 pinned and free layers are amorphous and the crystalline MgO tunnel barrier is formed by a ROX or NOX process. The capping layer preferably is a Hf/Ru composite where the lower Hf layer serves as an excellent oxygen getter material to reduce the magnetic “dead layer” at the free layer/capping layer interface and thereby increase dR/R, and lower He and Jc. The annealing temperature is lowered to about 280° C. to give a smoother CoFeB/MgO interface and a smaller offset field than with a 350° C. annealing. In a second embodiment, the AP1 layer has a CoFeB/CoFe configuration wherein the lower CoFeB layer is amorphous and the upper CoFe layer is crystalline to further improve dR/R and lower RA to ?10 ohm/?m2.

Abstract: An MTJ MRAM cell is formed by using a reactive ion etch (RIE) to pattern an MTJ stack on which there has been formed a bilayer Ta/TaN hard mask. The hard mask is formed by patterning a masking layer that has been formed by depositing a layer of TaN over a layer of Ta on the MTJ stack. After the stack is patterned, the TaN layer serves at least two advantageous purposes: 1) it protects the Ta layer from oxidation during the etching of the stack and 2) it serves as a surface having excellent adhesion properties for a subsequently deposited dielectric layer.

Abstract: A STT-MTJ MRAM cell that utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer includes an IrMn pinning layer, a SyAP pinned layer, a naturally oxidized, crystalline MgO tunneling barrier layer that is formed on an Ar-ion plasma smoothed surface of the pinned layer and a free layer that comprises an amorphous layer of Co60Fe20B20 of approximately 20 angstroms thickness or an amorphous ferromagnetic layer of Co40Fe40B20 of approximately 15 angstroms thickness formed between two crystalline layers of Fe of 3 and 6 angstroms thickness respectively. The free layer is characterized by a low Gilbert damping factor and by very strong polarizing action on conduction electrons. The resulting cell has a low critical current, a high dR/R and a plurality of such cells will exhibit a low variation of both resistance and pinned layer magnetization angular dispersion.

Abstract: An array of rows and columns of SMT MRAM cells has each of the columns associated with one of its adjacent columns. Each of the SMT MRAM cells of the column is connected to a true data bit line and each of the SMT MRAM cells of the associated pair of columns is connected to a shared complement data bit line. A shunting switch device is connected between each of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells.

Abstract: Methods are presented for fabricating an MTJ element having a uniform vertical distance between its free layer and a bit line and, in addition, having a protective spacer layer formed abutting the lateral sides of the MTJ element to eliminate leakage currents between MTJ layers and the bit line. Each method forms a dielectric spacer layer on the lateral sides of the MTJ element and, depending on the method, includes an additional layer that protects the spacer layer during etching processes used to form a Cu damascene bit line. At various stages in the process, a dielectric layer is also formed to act as a CMP stop layer so that the capping layer on the MTJ element is not thinned by the CMP process that planarizes the surrounding insulation. Subsequent to planarization, the stop layer is removed by an anisotropic etch of such precision that the MTJ element capping layer is not reduced in thickness and serves to maintain uniform vertical distance between the bit line and the MTJ free layer.

Abstract: An MRAM array structure and a method of its operation that is not subject to accidental writing on half-selected elements. Each element of the MRAM is an MTJ (magnetic tunneling junction) cell operating in accord with an STT (spin torque transfer) scheme for changing its free layer magnetization state and each cell is patterned to have a C-shape in the horizontal plane. The cell thereby operates by C-mode switching to provide stability against accidental writing by half-selection. During operation, switching of a cell's magnetization is accomplished with the assist of the pulsed magnetic fields of additional word lines that are formed either orthogonal to or parallel to the existing bit lines and that can carry currents in either direction as required to provide the assist.

Abstract: A dual spin filter that minimizes spin-transfer magnetization switching current (Jc) while achieving a high dR/R in STT-RAM devices is disclosed. The bottom spin valve has a MgO tunnel barrier layer formed with a natural oxidation process to achieve low RA, a CoFe/Ru/CoFeB—CoFe pinned layer, and a CoFeB/FeSiO/CoFeB composite free layer with a middle nanocurrent channel (NCC) layer to minimize Jc0. The NCC layer may have be a composite wherein conductive M(Si) grains are magnetically coupled with adjacent ferromagnetic layers and are formed in an oxide, nitride, or oxynitride insulator matrix. The upper spin valve has a Cu spacer to lower the free layer damping constant. A high annealing temperature of 360° C. is used to increase the MR ratio above 100%. A Jc0 of less than 1×106 A/cm2 is expected based on quasistatic measurements of a MTJ with a similar MgO tunnel barrier and composite free layer.

Abstract: A STT-RAM MTJ that minimizes spin-transfer magnetization switching current (Jc) is disclosed. The MTJ has a MgO tunnel barrier layer formed with a natural oxidation process to achieve a low RA (10 ohm-um2) and a Fe or Fe/CoFeB/Fe free layer which provides a lower intrinsic damping constant than a CoFeB free layer. A Fe, FeB, or Fe/CoFeB/Fe free layer when formed with a MgO tunnel barrier (radical oxidation process) and a CoFeB AP1 pinned layer in a MRAM MTJ stack annealed at 360° C. provides a high dR/R (TMR)>100% and a substantial improvement in read margin with a TMR/Rp_cov=20. High speed measurement of 100 nm×200 nm oval STT-RAM MTJs has shown a Jc0 for switching a Fe free layer is one half that for switching an amorphous CO40Fe40B20 free layer. A Fe/CoFeB/Fe free layer configuration allows the Hc value to be increased for STT-RAM applications.

Abstract: A magnetic sensor for identifying small magnetic particles bound to a substrate includes a regular, planar orthogonal array of MTJ cells formed within or beneath that substrate. Each MTJ cell has a high aspect ratio and positions of stable magnetic equilibrium along an easy magnetic axis and positions of unstable magnetic equilibrium along a hard magnetic axis. By initializing the magnetizations of each MTJ cell in its unstable hard-axis position, the presence of even a small magnetic particle can exert a sufficient perturbative strayfield to tip the magnetization to its stable position. The magnetization change in an MTJ cell can be measured after each of two successive opposite polarity magnetizations of a bound particle and the presence of the particle thereby detected.

Abstract: A BE patterning scheme in a MRAM is disclosed that avoids damage to the MTJ array and underlying ILD layer while reducing BE-BE shorts and BE-bit line shorts. A protective dielectric layer is coated over a MTJ array before a photoresist layer is coated and patterned on the dielectric layer. The photoresist pattern is transferred through the dielectric layer with a dielectric etch process and then through the BE layer with a metal etch that includes a certain amount of overetch to remove metal residues. The photoresist is stripped with a sequence involving immersion or spraying with an organic solution followed by oxygen ashing to remove any other organic materials. Finally, a second wet strip is performed with a water based solution to provide a residue free substrate. In another embodiment, a bottom anti-reflective coating (BARC) is inserted between the photoresist and dielectric layer for improved critical dimension control.

Abstract: A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.

Abstract: A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. A CoFeB layer may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.

Abstract: Formation of a bottom electrode for an MTJ device on a silicon nitride substrate is facilitated by including a protective coating that is partly consumed during etching of the alpha tantalum portion of said bottom electrode. Adhesion to SiN is enhanced by using a TaN/NiCr bilayer as “glue”.

Abstract: A method of forming a CPP MTJ MRAM element that utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer. The device includes a tunneling barrier layer of MgO and a non-magnetic CPP layer of Cu or Cr and utilizes a novel synthetic free layer having three ferromagnetic layers mutually exchange coupled in pairwise configurations. The free layer comprises an inner ferromagnetic and two outer ferromagnetic layers, with the inner layer being ferromagnetically exchange coupled to one outer layer and anti-ferromagnetically exchange coupled to the other outer layer. The ferromagnetic coupling is very strong across an ultra-thin layer of Ta, Hf or Zr of thickness preferably less than 0.4 nm.

Abstract: A MTJ that minimizes spin-transfer magnetization switching current (Jc) in a Spin-RAM to <1×106 A/cm2 is disclosed. The MTJ has a Co60Fe20B20/MgO/Co60Fe20B20 configuration where the CoFeB AP1 pinned and free layers are amorphous and the crystalline MgO tunnel barrier is formed by a ROX or NOX process. The capping layer preferably is a Hf/Ru composite where the lower Hf layer serves as an excellent oxygen getter material to reduce the magnetic “dead layer” at the free layer/capping layer interface and thereby increase dR/R, and lower He and Jc. The annealing temperature is lowered to about 280° C. to give a smoother CoFeB/MgO interface and a smaller offset field than with a 350° C. annealing. In a second embodiment, the AP1 layer has a CoFeB/CoFe configuration wherein the lower CoFeB layer is amorphous and the upper CoFe layer is crystalline to further improve dR/R and lower RA to ?10 ohm/?m2.

Abstract: A gate voltage boosting circuit provides a voltage boost to a gate of a select switching MOS transistor of a spin-torque MRAM cell to prevent a programming current reduction through an MTJ device of the spin-torque MRAM cell. A spin-torque MRAM cell array is composed of spin-torque MRAM cells that include a MTJ element and a select switching device. A local word line is associated with one row of the plurality of spin-torque MRAM cells and is connected to a gate terminal of the select switching devices of the row of MRAM cells to control activation and deactivation. One gate voltage boosting circuit is placed between an associated global word line and an associated local word line. The gate voltage boosting circuits boost a voltage of a gate of the selected switching device during writing of a logical “1” to the MTJ element of a selected spin-torque MRAM cell.

Abstract: Systems and methods for realizing current drivers without current or voltage feedback for devices that require accurate current drive with zero standby current has been disclosed. In a preferred embodiment of the invention this current driver is applied for write circuits for MRAMs. A fast and accurate reference current is generated by diode voltage divided by resistor without any feedback. The diode current is not fed back from the reference current. The diode current is generated from a regulated voltage. Temperature compensation of the write current is inherently built in the diode current reference. Fine-tuning of the temperature coefficient is achieved by mixing poly and diffusion resistors. A switch inserted in the current driver can turn on the driver fast and without a need for standby current. Leading boost in the current driver can fast charge the large coupling capacitance of word and bit lines and speed up write timing.