Abstract: A configurable MRAM device is achieved. The device comprises a memory array of magnetic memory cells. A first part of the array comprises the memory cells that can be accessed for reading and writing during normal operation. A second part of the array comprises the memory cells that can be read only during a power up initialization. The second part of the array is used to store configuration data for altering the physical operation of the memory array. Programmable current sources and timing delays use the stored configuration data to optimize device performance. A redundant section of memory cells is activated by the configuration data.

Abstract: A method to fabricate an MTJ device and its connections to a CMOS integrated circuit is described. The device is built out of three layers. The bottom layer serves as a seed layer for the center layer, which is alpha tantalum, while the third, topmost, layer is selected for its smoothness, its compatibility with the inter-layer dielectric materials, and its ability to protect the underlying tantalum.

Abstract: A random access memory cell is described which is capable of storing multiple information states in a single physical bit. The basic structure combines a conventional MTJ with a reference stack that is magnetostatically coupled to the MTJ. The MTJ is read in the usual way but data is written and stored in the reference stack. Through use of two bit lines, the direction of magnetization of the free layer can be changed in small increments each unique direction representing a different information state.

Abstract: An MRAM reference cell sub-array provides a mid-point reference current to sense amplifiers. The MRAM reference cell sub-array has MRAM cells arranged in rows and columns. Bit lines are associated with each column of the sub-array. A coupling connects the bit lines of pairs of the columns together at a location proximally to the sense amplifiers. The MRAM cells of a first of the pair of columns are programmed to a first magneto-resistive state and the MRAM cells of a second of the pair of columns are programmed to a second magneto-resistive state. When one row of data MRAM cells is selected for reading, a row of paired MRAM reference cells are placed in parallel to generate the mid-point reference current for sensing. The MRAM reference sub-array may be programmed electrically or aided by a magnetic field. A method for verifying programming of the MRAM reference sub-array is discussed.

Abstract: A super-paramagnetic cladding layer formed on from 1 to 3 sides of a conductive line in a magnetic device is disclosed. The cladding layer is made of “x” ML/SL stacks in which x is between 5 and 50, SL is an amorphous AlOx seed layer, and ML is a composite with a soft magnetic layer comprised of discontinuous particles less than 2 nm in size on the seed layer and a capping layer of Ru, Ta, or Cu on the soft magnetic layer. Fringing fields and hysteresis effects from continuous ferromagnetic cladding layers associated with switching the magnetic state of an adjacent MTJ are totally eliminated because of the super-paramagnetic character of the soft magnetic layer at room temperature. The soft magnetic layer has near zero magnetostriction, very high susceptibility, and may be made of Ni˜80Fe˜20, Ni˜30Fe˜70, Co˜90Fe˜10, or CoNiFe.

Abstract: A toggle MTJ cell is disclosed that has a nearly balanced SAF free layer with two major sub-layers separated by an anti-parallel coupling layer. Within each major sub-layer, there is a plurality of minor sub-layers wherein adjacent minor sub-layers are separated by a parallel coupling layer. The parallel coupling layer is a non-magnetic layer that may be a one or more of Ta, Cu, Cr, Ru, Os, Re, Rh, Nb, Mo, W, Ir, and V, a metal oxide, or dusting of NiCr, Ta, Cu, or NiFeCr. Magnetic moments of major sub-layers are made to be nearly equal so that the net moment of the SAF free layer is essentially zero. The MTJ cell and SAF free layer preferably have an aspect ratio of from 1 to 5. Ferromagnetic coupling between minor sub-layers enables a lower write current and lower power consumption than conventional toggle cell designs.

Abstract: A structure that is well suited to connecting an MTJ device to a CMOS integrated circuit is described. It is built out of three layers. The bottom layer serves as a seed layer for the center layer, which is alpha tantalum, while the third, topmost, layer is selected for its smoothness, its compatibility with the inter-layer dielectric materials, and its ability to protect the underlying tantalum. A method for its formation is also described.

Abstract: A method of forming a Cu—Cu junction between a word line pad (WLP) and bit line (BL) contact is described. An opening above a WL contact is formed in a first SiNx layer on a substrate that includes a WLP and word line. After a bottom electrode (BE) layer, MTJ stack, and hard mask are sequentially deposited, an etch forms an MTJ element above the word line. Another etch forms a BE and exposes the first SiNx layer above the WLP and bond pad (BP). An MTJ ILD layer is deposited and planarized followed by deposition of a second SiNx layer and BL ILD layer. Trenches are formed in the BL ILD layer and second SiNx layer above the WLP, hard mask and BP. After vias are formed in the MTJ ILD and first SiNx layers above the WLP and BP, Cu deposition follows to form dual damascene BL contacts.