Abstract: A method for performing timing analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Delay information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.

Abstract: A technique to verify, evaluate, and estimate the performance of an integrated circuit is embodied in a computer software program that is executable by a computer system. When estimating performance, the invention partitions an integrated circuit into strongly coupled components. The technique accurately estimates of the performance (e.g., transient delays) of an integrated circuit, and has fast execution times. The technique is applicable to small circuits having relatively few transistors, and especially well suited for integrated circuits having millions of transistors and components. The technique handles the effects of deep-submicron integrated circuit technology.

Abstract: A method for designing integrated circuits includes receiving a floorplan design associated with an integrated circuit. A relative floorplanning constraint is extracted from the floorplan design. The floorplan of the integrated circuit is updated in response to the relative floorplanning constraint. Another method for designing integrated circuits includes receiving a floorplan design associated with an integrated circuit. A set of relative floorplanning constraint is received from the floorplan design. A relative floorplanning constraint is pushed down from the set of relative floorplanning constraints into a partition associated with the floorplan of the integrated circuit. The floorplan is updated in response to the set of relative floorplanning constraints.

Abstract: An electronic design automation method of placing circuit components of an integrated circuit (“IC”) is provided. A synthesized circuit netlist including one or more soft macros is received and a rough global placement of this netlist is performed. A shaper function is determined. The shaper function evaluates a cost of a current placement of the one or more soft macros based on one or more constraints and one or more penalty functions which are associated with the one or more constraints. Moreover, the current placement is optimized to produce a subsequent placement of the one or more soft macros by minimizing the cost. Furthermore, where the netlist includes one or more hard macros, a legalization requirement is applied to the one or more hard macros.

Abstract: An integrated circuit and a method for using metal fill geometries to reduce the voltage drop in power meshes. Metal fill geometries are connected to the power mesh using vias or wires at multiple locations. Metal fill geometries are connected to other floating metal fill geometries using vias or wires at multiple locations. The circuit design introduces maximum redundancy between metal fill geometries and power mesh geometries, but partial redundancy between metal fill geometries and metal fill geometries. In particular, the redundancy in connectivity between metal fill geometries and metal fill geometries is kept minimal to reduce the number of geometries introduced. The high redundancy between metal fill geometries and power mesh geometries and the partial redundancy among metal fill geometries result in a smaller IR-drop by reducing the effective resistance on a power mesh.

Abstract: Methods for floorplanning a hierarchical physical design to improve placement and routing are provided and described. In one embodiment, a method of floorplanning a hierarchical physical design includes arranging a plurality of blocks in a top-level of the hierarchical physical design. Each block includes a plurality of linear edges. Additionally, at least one of the blocks is selected. Furthermore, at least one linear edge of the selected block is rasterized. This rasterization includes converting the linear edge to a stepped-shape edge.

Abstract: Aspects of the present invention include a methodology for the general timing-driven iterative refinement-based approach, a timing-driven optimization (TDO) method that optimizes the circuit depth after the area oriented logic optimization, and a layout-driven synthesis flow that integrates performance-driven technology mapping and clustering with TDO to account for the effect of mapping and clustering during the timing optimization procedure of TDO. The delay reduction process recursively reduces the delay of critical fanins of a selected. Furthermore, in one embodiment, the fanins of the selected node are sorted according to their slack values.

Abstract: A system and a method are disclosed for performing a timing or signal propagation delay analysis on a circuit. The disclosure includes representing a drive logic stage as a representative linear circuit driven by a current source. The current source is represented as a function of a current at a constant value, a start time, a tail-start time, and a time constant of an equivalent capacitive circuit. Once the current source model is constructed, a logic stage can be analyzed for timing or signal propagation delay using conventional linear circuit analysis techniques. The disclosure also is applicable to resistance capacitance (“RC”) interconnect circuits using a current source model in which an RC load is represented as an effective capacitance and the current source for use in a linear analysis is constructed using an iterative approach.

Abstract: A memory logic built-in self-test (“BIST”) includes slow speed controller-to-collar signals, while allowing collars to test memories at full speed. A controller is configured to include control features and address, data, read/write, output evaluation, and redundancy calculation values are configured within the collars. The controller is further configured to handle scheduling of the collars and diagnostics interfacing. In addition, the collars are configured to allow BIST testing to be run serially, in parallel, or in groups. Collars are also configured to send diagnostic results back to the controller based on the initialization of the respective collars, thus providing a central interface for the diagnostics results.

Abstract: Methods of creating a power distribution arrangement with tapered metal wires for a physical design are provided and described. In one embodiment, a method of creating a power distribution arrangement for a physical design of an integrated circuit includes arranging a plurality of metal wires for power distribution in a desired arrangement. Each metal wire has a width. Furthermore, the metal wires are tapered such that the width is thicker in a core edge area of the physical design than in a core center area of the physical design. In other embodiments, a method of creating a power distribution arrangement for a physical design of a current integrated circuit includes arranging a plurality of metal wires for power distribution in a desired arrangement. The metal wires are tapered using a routing congestion profile and/or a voltage drop profile of a prior physical design of a prior integrated circuit.

Abstract: Subtleties of advanced fabrication processes and nano-scale phenomena associated with integrated circuit miniaturization have exposed the insufficiencies of design rules. Such inadequacies have adverse impact on all parts of the integrated circuit creation flow where design rules are used. In addition, segregation of the various layout data modification steps required for deep sub-micrometer manufacturing are resulting in slack and inefficiencies. This invention describes methods to improve integrated circuit creation via the use of a unified model of fabrication processes and circuit elements that can complement or replace design rules. By capturing the interdependence among fabrication processes and circuit elements, the unified model enables efficient layout generation, resulting in better integrated circuits.

Abstract: Methods for floorplanning a hierarchical physical design to improve placement and routing are provided and described. In one embodiment, a method of floorplanning a hierarchical physical design includes arranging a plurality of blocks in a top-level of the hierarchical physical design. Each block includes a plurality of linear edges. Additionally, at least one of the blocks is selected. Furthermore, at least one linear edge of the selected block is rasterized. This rasterization includes converting the linear edge to a stepped-shape edge.

Abstract: A basic Boolean circuit is a transistor circuit commonly used in industry to produce the logic of a particular Boolean gate. A sequence of standard Boolean circuits disposed along the processing path of an integrated circuit define a predetermined truth table representing the relationship of inputs and outputs of the processing path. A reduced-transistor circuit is generated that is defined by the same truth table as the sequence of standard Boolean logic circuits, but is not definable by a sequence of standard Boolean logic circuits. A processing path of an integrated circuit is programmed with the reduced-transistor circuit instead of the sequence of standard Boolean circuits, thereby reducing the time delay of the processing path and the power consumed by the circuit. The reduced-transistor circuit may be generated in response to receiving a programming instruction defining a sequence of Boolean gates.

Abstract: A technique to verify, evaluate, and estimate the performance of an integrated circuit is embodied in a computer software program that is executable by a computer system. To estimate performance, the integrated circuit design is partitioned into strongly coupled components and state points are identified. The technique accurately estimates of the performance (e.g., transient delays) of an integrated circuit, and has fast execution times. The technique is applicable to small circuits having relatively few transistors, and especially well suited for integrated circuits having millions of transistors and components. The technique handles the effects of deep-submicron integrated circuit technology.

Abstract: Methods for generating a padring layout design are described. These methods utilize automation while still allowing customization. Automation is emphasized as much as possible so that more time can be used to solve the various problems that make each padring layout design unique. A framework in which regular patterns can be described, replicated, and tailored is provided. The padring is broken down into zones in which slots having bumps/bond pads areas, I/O cell areas, and/or edge logic cell areas are laid out in a regular pattern through an instantiation process. Edge logic, which is comprised of standard cells, is pulled from the core of the chip because these cells couple directly to I/O cells and are critical for timing.

Abstract: A method for modeling integrated circuit designs in a hierarchical design automation system which utilizes a block abstraction including therein set of all database objects (cells, nets, wires, vias, and blockages) that are necessary to achieve accurate placement, routing, extraction, simulation, and verification of the block's ancestors in the hierarchy.

Abstract: A process for reducing cross-talk noise in a VLSI circuit is disclosed. The process identifies a victim net in an integrated circuit and calculates a change in ground capacitance for the victim net to identify a noise amplitude less than or equal to a maximum allowable noise height. The process selects from a library one cell or a grouping of cells having an input capacitance for the victim net closest to the change in ground capacitance. The selected cell or grouping of cells is coupled to the victim net so that its change in ground capacitance provides a noise amplitude less than (or less than or equal to) an allowable maximum noise height that may be a predetermined value. A system for reducing cross-talk noise in a VLSI circuit is also disclosed.

Abstract: A method and apparatus for identifying potential noise failures in an integrated circuit design is described. In one embodiment, the method comprises locating a victim net and an aggressor within the integrated circuit design, modeling the victim net using two ?-type resistor-capacitor (RC) circuits, including determining a coupling between the victim net and the aggressor, and indicating that the integrated circuit design requires modification if modeling the victim net indicates that a potential noise failure may occur in the integrated circuit design.

Abstract: A technique to verify, evaluate, and estimate the performance of an integrated circuit is embodied in a computer software program that is executable by a computer system. Vectors are generated to estimate integrated circuit performance. The technique accurately estimates of the performance (e.g., transient delays) of an integrated circuit, and has fast execution times. The technique is applicable to small circuits having relatively few transistors, and especially well suited for integrated circuits having millions of transistors and components. The technique handles the effects of deep-submicron integrated circuit technology.

Abstract: A fast method of estimating capacitances and wire delays in an integrated circuit design is based on placement information such as that contained in a gate schematic net list from a logic synthesis tool. A simple tree topology called a spine tree is constructed to connect the pins of the net as an approximation of actual connections therein. Capacitance is extracted for this topology assuming a worst case scenario, and Elmore delays are computed for the wire delays based on the worst-case capacitances. The method takes linear time as a function of the number of pins in the net and is much faster than using a Steiner tree method in this context.