Abstract: The display device includes a display panel including a plurality of pixels; a driver IC configured to convert digital data corresponding to an input image to an analog voltage using a gamma voltage, and to supply the analog voltage to the plurality of pixels; and a power supply configured to supply a pixel driving voltage to the display panel and the driver IC. The driver IC includes a weight selector configured to select a weight for adjusting the gamma voltage based on a change amount of the pixel driving voltage supplied from the power supply; and a gamma reference voltage generating unit configured to generate a gamma reference voltage based on the selected weight.

Abstract: A source buffer output switch control circuit for controlling operations of a source buffer output switch configured to transmit a source signal output from a source buffer to a display panel or block the source signal includes: a switch driver configured to generate a switch control signal for controlling the operations of the source buffer output switch based on a switch operation input signal; a current limiter configured to limit a driving current applied to the switch driver in order to control a slew rate of the switch control signal; and a bias block configured to supply the current limiter with a bias voltage for controlling a magnitude of the driving current.

Abstract: A display driving device includes a timing controller and a charge pump configured to output a pump voltage for driving a source driver. The charge pump includes a flying capacitor; a first switch disposed between one end of the flying capacitor and a first terminal; a second switch disposed between the one end of the flying capacitor and a second terminal; a third switch disposed between another end of the flying capacitor and a third terminal; a fourth switch disposed between the another end of the flying capacitor and a fourth terminal; and a charge pump control unit configured to control turning on or off of the first to the fourth switches based on the anti-tearing signal, and control the first to the fourth switches based on the anti-tearing signal to operate in a first mode or a second mode configured to reduce power consumption than in the first mode.

Abstract: A display driving device includes a timing controller and a charge pump configured to output a pump voltage for driving a source driver. The charge pump includes a flying capacitor; a first switch disposed between one end of the flying capacitor and a first terminal; a second switch disposed between the one end of the flying capacitor and a second terminal; a third switch disposed between another end of the flying capacitor and a third terminal; a fourth switch disposed between the another end of the flying capacitor and a fourth terminal; and a charge pump control unit configured to control turning on or off of the first to the fourth switches based on the anti-tearing signal, and control the first to the fourth switches based on the anti-tearing signal to operate in a first mode or a second mode configured to reduce power consumption than in the first mode.

Abstract: A buffer circuit includes an input stage configured to provide a differential current to a load stage or receive the differential current from the load stage based on a difference between an input voltage and an output voltage, wherein the load stage is configured to apply gate voltages to first and second output transistors of an output stage, and wherein the output stage is configured to regulate the output voltage; a slew rate compensation circuit configured to provide a slew rate compensation current to the load stage or receive the slew rate compensation current from the load stage; an offset control signal output stage configured to output an offset control signal by being applied with first and second N-bit control signals; and an offset blocking circuit comprising a switch configured to turn off a current source of the slew rate compensation circuit by the offset control signal.

Abstract: An electronic device includes a first electronic device including a signal generator configured to generate signals for a first calibration using a first pattern, and a second calibration using a random pattern; and a second electronic device. The second electronic device includes a signal processor configured to process reception data transmitted from the first electronic device; a pattern generator configured to generate pattern data for the second calibration; a re-synchronization point generator configured to generate re-synchronization point data to recover a noisy clock signal during the second calibration; and a calibration performer configured to perform the second calibration using the reception data, the pattern data, and the re-synchronization point data.

Abstract: A mask layout for forming a semiconductor device includes an active mask pattern, a gate electrode mask pattern, a silicide blocking mask pattern, and a contact mask pattern. The active mask pattern forms source and drain regions in a substrate. The gate electrode mask pattern, disposed to overlap the active mask pattern, forms a gate electrode between the source region and the drain region. The silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern in the gate electrode, the source region, and the drain regions to form a silicide blocking region. The contact mask pattern, disposed spaced apart from the silicide blocking mask pattern, forms a contact plug on the substrate. The silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.

Abstract: A semiconductor device includes a source region, a drain region, and a gate dielectric layer formed on a substrate; a gate electrode formed on the gate dielectric layer; a first dielectric pattern, formed contacting a sidewall of the gate electrode, extending from the source region to a portion of an upper surface of the gate electrode; a spacer formed on another sidewall of the gate electrode between the gate electrode and the drain region; and a gate silicide layer formed between the first dielectric pattern and the spacer.

Abstract: A slew rate acceleration circuit in a buffer circuit, is configured at least to detect a current flowing through a load stage of the buffer circuit, compare a value of the detected current with a reference value, and supply an adjusting driving voltage to an output stage of the buffer circuit based on results of the comparison for increasing a slew rate of the buffer circuit.

Abstract: A display panel driving device includes a control IC, a power management integrated circuit (PMIC), and a digital circuit unit configured to drive a display panel. The digital circuit unit is supplied with an adjusted external power supply voltage according to a load mode of the digital circuit unit to control driving of the display panel, and the control IC is configured to control the PMIC according to the load mode and enable the external power supply voltage to be variably supplied to the digital circuit unit according to the control operation of the control IC.

Abstract: A power factor correction circuit includes an inductor configured to receive an input voltage and supply an output voltage; a power switch connected to the inductor and configured to control an input current flowing through the inductor; and a switch controller configured to receive a feedback voltage including information on the output voltage and an auxiliary voltage including information on a voltage of the inductor and control an on/off operation of the power switch. The switch controller is further configured to operate in a first mode when the feedback voltage is less than a reference voltage, and operate in a second mode when the feedback voltage is greater than the reference voltage.

Abstract: A switch control circuit and switch control method are provided. The switch control circuit and switch control method compensate an error of a load current that occurs because of the changing of a slope of an inductor current based on the increase and decrease of an input voltage. The switch control circuit includes a current compensation device that adjusts a gate on time based on a RC resistor and a control signal that senses a gate terminal of a control switch. The current compensation device compensates an error that occurs due to a signal delay to a gate terminal by increasing or decreasing a reference voltage or a sensing voltage, according to an increase or a decrease of an input voltage.

Abstract: A buffer circuit that generates an output voltage based on an input voltage includes an input stage configured to provide a differential current to a load stage based on a difference between the input voltage and the output voltage; the load stage configured to apply gate voltages to output transistors of an output stage based on the differential current; the output stage configured to regulate the output voltage based on the gate voltages applied to the output transistors; and a slew rate compensator configured to provide a first slew rate compensation current and a second slew rate compensation current to the load stage or receive the first slew rate compensation current and the second slew rate compensation current from the load stage based on the difference between the input voltage and the output voltage.

Abstract: A buffer circuit for generating an output voltage according to an input voltage includes: an input stage configured to provide a first differential current to a load stage or receive a second differential current from the load stage based on a difference between the input voltage and the output voltage; the load stage configured to apply gate voltages to a first output transistor and a second output transistor of an output stage based on the first differential current or the second differential current; the output stage configured to regulate the output voltage based on the gate voltages applied to the first output transistor and the second output transistor; and a slew rate compensator configured to provide a source current to the load stage or receive a sink current from the load stage to regulate the gate voltages of the first output transistor and the second output transistor.

Abstract: A switch control circuit and switch control method are provided. The switch control circuit and switch control method compensate an error of a load current that occurs because of the changing of a slope of an inductor current based on the increase and decrease of an input voltage. The switch control circuit includes a current compensation device that adjusts a gate on time based on a RC resistor and a control signal that senses a gate terminal of a control switch. The current compensation device compensates an error that occurs due to a signal delay to a gate terminal by increasing or decreasing a reference voltage or a sensing voltage, according to an increase or a decrease of an input voltage.

Abstract: A spread spectrum clock generation device that may reduce electromagnetic interference (EMI) includes: a first comparator configured to compare an input signal with a first reference voltage and output a first comparison signal; a second comparator configured to compare the input signal with a second reference voltage and output a second comparison signal; a latch configured to receive the first and second comparison signals as inputs and output an output signal; and a delaying circuit configured to generate the input signal by delaying the output signal to have a different delay time for each time interval.

Abstract: A source buffer output switch control circuit for controlling operations of a source buffer output switch configured to transmit a source signal output from a source buffer to a display panel or block the source signal includes: a switch driver configured to generate a switch control signal for controlling the operations of the source buffer output switch based on a switch operation input signal; a current limiter configured to limit a driving current applied to the switch driver in order to control a slew rate of the switch control signal; and a bias block configured to supply the current limiter with a bias voltage for controlling a magnitude of the driving current.

Abstract: A mask layout for forming a semiconductor device includes an active mask pattern, a gate electrode mask pattern, a silicide blocking mask pattern, and a contact mask pattern. The active mask pattern forms source and drain regions in a substrate. The gate electrode mask pattern, disposed to overlap the active mask pattern, forms a gate electrode between the source region and the drain region. The silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern in the gate electrode, the source region, and the drain regions to form a silicide blocking region. The contact mask pattern, disposed spaced apart from the silicide blocking mask pattern, forms a contact plug on the substrate. The silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.

Abstract: A mask layout for forming a semiconductor device includes an active mask pattern, a gate electrode mask pattern, a silicide blocking mask pattern, and a contact mask pattern. The active mask pattern forms source and drain regions in a substrate. The gate electrode mask pattern, disposed to overlap the active mask pattern, forms a gate electrode between the source region and the drain region. The silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern in the gate electrode, the source region, and the drain regions to form a silicide blocking region. The contact mask pattern, disposed spaced apart from the silicide blocking mask pattern, forms a contact plug on the substrate. The silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.