Abstract: A combined serial priority and parallel priority apparatus and method of operation for use in data processing systems. Each of the parallel priority circuits are interconnected by a common parallel priority bus which carries parallel priority signals indicating the priority level of any unit requesting access. If a unit requesting access has a lower priority than indicated on the parallel priority bus, that requesting unit is inhibited from obtaining access. If a requesting unit has higher priority than the signals on the parallel priority bus, that unit in turn causes the priortiy bus to be switched to the higher priority level.The serial priority circuits act together with other serial priority circuits within a group of priority circuits set to the same parallel priority. In this configuration, the parallel priority circuits perform a high-order priority determination while the serial priority circuits perform a low-order priority determination.

Abstract: A microinstruction-controlled computer including a sequencer for controlling the sequencing of microinstructions. The computer executes target instructions by executing a number of microinstructions for each target instruction. Microinstructions are grouped in one or more microinstruction subroutines in a microstore. Microaddresses for addressing microinstructions and subroutines in the microstore are provided by a microaddress generator which includes a stack unit and other microaddress sources. The stack unit includes a stack memory and a link memory. The link memory stores, for each target instruction, a predetermined number of preloaded microaddresses where each such microaddress specifies the address of one of a number of subroutines employed to execute a particular target instruction. Sequential microaddresses in the link memory are accessed to link the subroutines employed in the execution of each target instruction.