Abstract: In one embodiment of the invention, there is provided a tool for annealing a magnetic stack. The tool includes a housing defining a heating chamber; a holding mechanism to hold at least one wafer in a single line within the heating chamber, a heating mechanism to heat the at least one wafer; and a magnetic field generator to generate a magnetic field whose field lines pass through the single line of wafers during a magnetic annealing process; wherein the holding mechanism comprises a wafer support of holding the single line of wafers between the heating mechanism and the magnetic field generator. The tool may be a rapid thermal processor retrofitted with the magnetic field generator.

Abstract: A magnetic memory cell is provided. The cell comprises first and second free layers; and an intermediate layer separating the first and second free layers, wherein the first and second free layers are magnetostatically coupled.

Abstract: Memory cell comprising two conductors, with a serially connected magnetic storage element and a Schottky diode between the two conductors. The Schottky diode provides a unidirectional conductive path between the two conductors and through the element. The Schottky diode is formed between a metal layer in one of the two conductors and a processed junction layer. Methods for process and for operation of the memory cell are also disclosed. The memory cell using the Schottky diode can be designed for high speed operation and with high density of integration. Advantageously, the junction layer can also be used as a hard mask for defining the individual magnetic storage element in the memory cell. The memory cell is particularly useful for magnetic random access memory (MRAM) circuits.

Abstract: Disclosed is a memory circuit and method of forming the same. The memory circuit comprises a lower metallization layer defining first conducting lines. A continuous magnetic storage element stack is atop the lower metallization layer wherein a bottom electrode of the stack is in direct contact with the first conducting lines. An upper metallization layer is atop the continuous magnetic storage element stack, the upper metallization layer defining second conducting lines, which are in direct contact with said continuous magnetic storage element stack. Localized areas of the continuous magnetic storage element stack define discrete magnetic bits, each energizable through a selected pair of the first and second conducting lines. In a second aspect and a third aspect, the continuous magnetic storage element stack is respectively partially and fully etched through a single mask, to define the discrete magnetic bits.

Abstract: A method for fabricating a circuit, by defining a first set of resist features on a substrate and corresponding to a first mask layout, followed by defining a second set of resist features on the substrate corresponding to a second mask layout, wherein the second set adds to the first set for rectifying an error in either mask layout. In another aspect, the method is by defining a first set of resist features on a substrate and corresponding to a first mask layout that has an error, etching the substrate while the first set protects selected regions, defining a second set of resist features on the substrate and corresponding to a second mask layout, followed by etching the substrate to selectively remove portions of the selected regions for rectifying the error.

Abstract: In one embodiment, there is provided a non-volatile magnetic memory cell. The non-volatile magnetic memory cell comprises a switchable magnetic element; and a word line and a bit line to energize the switchable magnetic element; wherein at least one of the word line and the bit line comprises a magnetic sidewall that is discontinuous.

Abstract: Magnetic memory cell comprising two conductors and a magnetic storage element between the two conductors, wherein a magnetic enhancement layer (MEL) is provided in the proximity of at least along a partial length of at least one of the two conductors. The MEL is for enhancing a magnetic field in the element when the two conductors are energized. Methods for operation and fabrication process for the memory cell are also disclosed. The memory cell is particularly for use in magnetic random access memory (MRAM) circuits, when using magnetic tunnel junction (MTJ) stacks as the magnetic storage elements.

Abstract: In one embodiment, there is provided a non-volatile magnetic memory cell. The non-volatile magnetic memory cell comprises a switchable magnetic element; and a word line and a bit line to energize the switchable magnetic element; wherein at least one of the word line and the bit line comprises a magnetic sidewall that is discontinuous.

Abstract: A semiconductor integrated circuit comprising a first circuit area for a low voltage operation and a second circuit area for a high voltage operation. The circuit areas comprise two vertically stacked backend patterned metal layers that are separated by an inter-metallic dielectric (IMD). The two metal layers and the IMD form a combination that is operable at the low voltage. The first circuit area uses a first portion of the combination for operating at the low voltage and the second circuit area uses a second portion of the combination for routing at the high voltage, the two metal layers in the second portion being interconnected through the IMD by via hole, for withstanding the high voltage. The first portion may comprise an array of magnetic random access memory (MRAM) devices and the second circuit area may comprise a display drive circuit.

Abstract: Magnetic memory cell comprising two conductors and a magnetic storage element between the two conductors, wherein a magnetic enhancement layer (MEL) is provided in the proximity of at least along a partial length of at least one of the two conductors. The MEL is for enhancing a magnetic field in the element when the two conductors are energized. Methods for operation and fabrication process for the memory cell are also disclosed. The memory cell is particularly for use in magnetic random access memory (MRAM) circuits, when using magnetic tunnel junction (MTJ) stacks as the magnetic storage elements.

Abstract: A semiconductor integrated circuit comprising a first circuit area for a low voltage operation and a second circuit area for a high voltage operation. The circuit areas comprise two vertically stacked backend patterned metal layers that are separated by an inter-metallic dielectric (IMD). The two metal layers and the IMD form a combination that is operable at the low voltage. The first circuit area uses a first portion of the combination for operating at the low voltage and the second circuit area uses a second portion of the combination for routing at the high voltage, the two metal layers in the second portion being interconnected through the IMD by via hole, for withstanding the high voltage. The first portion may comprise an array of magnetic random access memory (MRAM) devices and the second circuit area may comprise a display drive circuit.

Abstract: A current driving mechanism for a magnetic memory device, comprising: a) a current driver circuit; and b) a current decoding block coupled to the current driver circuit, wherein the current decoding block comprises a transistor (M18) to control driver currents from the current driver circuit, and wherein the transistor (M18) has a smaller form factor then otherwise possible by virtue of maintaining a gate thereof at a negative voltage.

Abstract: A memory circuit comprising a set of longitudinal conducting lines and a set of transverse conducting lines, wherein, each conducting line comprises alternating regions of reduced and increased line widths. The set of transverse conducting lines overlies the set of longitudinal conducting lines to define crossover zones wherein the reduced line width regions of the transverse conducting lines cross over the reduced line width regions of the longitudinal conducting lines. The circuit further comprises addressable magnetic storage elements, each disposed within a crossover zone between a longitudinal conducting line and a transverse conducting line thereof. The reduced line width regions improve magnetic flux efficiency in the magnetic storage elements and the increased line width regions lower the resistance in the conducting lines.

Abstract: Disclosed is a nonvolatile magnetic memory cell, comprising: a) a switchable magnetic element; b) a word line and a bit line to energize the switchable magnetic element; and c) a magnetic field boosting material positioned adjacent to at least one of the word line and the bit line to boost a magnetic field generated by current flowing therein.

Abstract: A horizontally disposed elliptical or rectangular magnetic memory cell includes at least two conductive lines to carry current and a magnetic element disposed between the conductive lines. The current through the conductive lines induces a magnetic field, such that the magnetic element is directly accessible. The magnetic memory cell can be sensed with a GMR head.

Abstract: Embodiments of the invention magnetic memory device, comprising: a magnetic tunnel junction (MTJ) which includes a first free layer optimized for reading; and a second free layer separate from the MTJ and optimized for writing.

Abstract: A magnetic memory cell in which a sensor is magnetically coupled to a magnetic media wherein the separation of the magnetic media from the sensor permits each to be magnetically optimized separate from the other, thus improving defect tolerance and minimizing the magnetic influence of neighboring cells in an array on one another. In an embodiment, the read circuitry is positioned so that no read current passes through the media during a read operation. In an alternative embodiment, processing is simplified but the read current is allowed to pass through the media.

Abstract: Embodiments of the invention provide compact magnetic random access memory cell, comprising a word line; a bit line comprising a slot formed therein; a magnetic storage element disposed between the word line and the bit line; an access transistor located below the bit line and aligned with the slot therein; and a conductor passing through the slot in the bit line electrically connect the magnetic storage element to the access transistor.

Abstract: In one embodiment, there is provided a method for programming a memory device having magnetoresistive memory elements as storage elements. The method is performed during fabrication of the memory device and may be used to realize a Magnetic Read Only Memory (MROM) device. In accordance with the method, during fabrication of a memory device comprising a plurality of magnetoresistive memory elements (MRME) e.g. a MTJs, the memory device is programmed by selectively controlling the presence or absence of the magnetoresistive element at each intersection of a word line (WL) and a bit line (BL) in the device.

Abstract: Embodiments of the present invention disclose an MRAM device having a plurality of magnetic memory cells grouped into words, and write conductors for carrying write currents to write to the memory cells, wherein at least some of the write conductors have a reduced cross-sectional area in the vicinity of a group of memory cells.