Abstract: A binary comparison circuit in which the comparison of individual bits of binary signals can be overridden, with the comparisons of the remaining non-overridden bits determining logical equivalence of the binary signals. This enables the binary signals being compared to be analyzed when they are not fully logically equivalent. In the preferred embodiment, the comparisons of all but the least significant bit are overridable. The circuit may be constructed by programming PAL (Programmable Array Logic) devices.

Abstract: A method and circuitry are disclosed for monitoring the performance of a switching system such as a switch mode converter by monitoring the duty cycle of the system. With respect to a switch mode converter, its duty cycle is a parameter which determines whether or not the converter is in jeopardy of loosing its ability to regulate an output voltage. As long as the duty cycle of the converter is below a given threshold, which may approach 100 percent, the converter has the ability to continue regulating the output voltage. The method and circuitry disclosed herein monitor a signal of the converter having a duty cycle related to the duty cycle of the converter and provide a signal indicating when the duty cycle of the converter is equal to or greater than a predetermined threshold duty cycle.

Abstract: A switch mode converter is disclosed which has an improved base drive therefor. The switch mode converter includes a pair of primary transistor switches each of which is connected to a transformer having a feedback winding connected to the respective transistor in a proportional base drive configuration. A controller circuit controls a switch connected in series with the primary winding of each transformer to switch the current supplied to the primary winding of each transformer from first and second current supplying circuits. Each second current supplying circuit temporarily supplies current to the transformer during the time that the respective transistor is being switched off to shorten the turn-off time of the transistor. The second current supplying circuits are coupled to the output of the primary switches and each is supplied with energy only when the respective transistor is switched on, and therefore do not saturate the transformer or continuously dissipate power.

Abstract: A method and circuitry are disclosed for ensuring that cross-conduction of a pair of primary switches coupled across a DC input voltage in a switch mode converter does not occur based on the actual state of the primary switches. The DC input is coupled to the output of the primary switches through a respective primary switch during first and second time periods in respective half cycles of the converter. Each first and second time period is separated by a deadband during which signals are provided to turn each primary switch off. The state of the primary switches is monitored during the deadband, and the deadband is maintained before progressing into the next first or second time period until both primary switches of the pair are off. Converters utilizing the method and circuitry for accomplishing the foregoing are also disclosed.

Abstract: A memory request arbitrator is provided for selecting one of a plurality of requesting devices, such as microprocessors, which may make a request to access a memory device common to the plurality of requestors. Requests from the devices are applied in common as a portion of an address to a read only memory, a priority sequencer providing another portion of the address. The read only memory provides a selection signal to the selected requestor. The priority sequencer is periodically updated to thereby change the priority of requestors such that priority is given to each of the requestors over time. The priority sequencer may be temporarily disabled to thereby allow a requestor a "back-to-back" memory access for a multi-cycle memory instruction. Finally, the initial state of the request lines is checked upon system start up to determine whether any of the request lines are unused. Only those request lines associated with presently operating requestors are able to provide request signals to the read only memory.