Patents Assigned to MangnaChip Semiconductor, Ltd.
  • Patent number: 7452802
    Abstract: Disclosed herein is a method of forming metal wirings for high voltage elements. According to the present invention, after a copper film is formed, a wet etch process using an interlayer insulating film as an etch mask is performed to pattern the copper film. It is thus possible to form copper wirings for high voltage elements the width of which is very wide. Furthermore, a wet etch process using a chemical aqueous solution is performed instead of a copper polishing process. The cost for forming a metal wiring can be thus saved. Moreover, by controlling a wet etch time, the space between metal wirings, which is narrower than a width of the metal wiring, can be secured sufficiently.
    Type: Grant
    Filed: January 7, 2005
    Date of Patent: November 18, 2008
    Assignee: MangnaChip Semiconductor, Ltd.
    Inventor: Ihl Hyun Cho
  • Publication number: 20050153549
    Abstract: Disclosed herein is a method of forming metal wirings for high voltage elements. According to the present invention, after a copper film is formed, a wet etch process using an interlayer insulating film as an etch mask is performed to pattern the copper film. It is thus possible to form copper wirings for high voltage elements the width of which is very wide. Furthermore, a wet etch process using a chemical aqueous solution is performed instead of a copper polishing process. The cost for forming a metal wiring can be thus saved. Moreover, by controlling a wet etch time, the space between metal wirings, which is narrower than a width of the metal wiring, can be secured sufficiently.
    Type: Application
    Filed: January 7, 2005
    Publication date: July 14, 2005
    Applicant: MangnaChip Semiconductor, Ltd.
    Inventor: Ihl Cho
  • Publication number: 20050090035
    Abstract: A method for fabricating a complementary metal oxide semiconductor image sensor is capable of protecting a low temperature oxide from delaminating a passivation layer. The method includes the steps of: forming a passivation layer on a pad metal; exposing a predetermined part of the pad metal by patterning the passivation layer using a first pad mask; forming an oxide layer on the exposed pad metal and the passivation layer formed around the pad open region; forming a color filter, a planarization layer and a microlens, sequentially; forming a low temperature oxide layer on the above structure to protect the microlens; and opening the pad metal by selectively etching the low temperature oxide layer and the oxide layer formed around the pad open region by a second pad mask.
    Type: Application
    Filed: October 22, 2004
    Publication date: April 28, 2005
    Applicant: MangnaChip Semiconductor, Ltd.
    Inventor: Eun-Ji Kim